Pipelining Summary

Introduction to Pipelining

  • Pipelining overlaps execution of multiple instructions, improving throughput.

Concept of Pipelining

  • Pipelining stages must operate concurrently.

  • Example of laundry illustrates pipelining: multiple loads processed simultaneously.

  • Speed-up from pipelining is equal to the number of stages if each stage takes the same time.

Pipelining in Processors

  • Classic MIPS instruction execution stages:

    1. Fetch instruction from memory (IF)

    2. Decode instruction (ID)

    3. Execute operation (EX)

    4. Memory access (MEM)

    5. Write register (WB)

  • Effectively a five-stage pipeline.

Pipelining Speedup Formula

  • Under ideal conditions, speed-up is close to the number of stages, but actual speed-up is less due to overhead.

Pipelining Hazards

  • Hazards prevent next instruction from executing; three types are identified:

    1. Structural hazards: hardware resource conflicts.

    2. Data hazards: next instruction depends on the result of a prior instruction.

    3. Control hazards: decision-making based on instruction execution.

Solutions to Hazards

  • Structural: separate instruction and data memory.

  • Data: use forwarding/bypassing to resolve data dependencies without waiting.

  • Control: employ stalling or branch prediction methods to manage instruction flow.

Branch Prediction Techniques

  • Dynamic predictors utilize past behavior for future prediction, achieving over 90% accuracy.

  • Incorrect predictions can cause pipeline disruptions, requiring restart from correct address.

Example of Implementation

  • Calculation of sequential vs parallel execution times provides insight into pipelining efficiency, with speed-up calculation showing significant performance improvement.