Comprehensive Study Guide for IGCSE and O Level Computer Science

DATA REPRESENTATION\n\n## 1.1 Number Systems\n\n### 1.1.1 Binary\n* Fundamentals: The binary system is the basic building block of all computers. It is a base 2 number system consisting only of $1$s and $0$s.\n* Digital Switches: Computers contain millions of tiny switches. A switch in the ON position is represented by $1$; OFF is represented by $0$.\n* Logic Gates: These switches use logic gates to store and process data.\n\n### 1.1.2 Binary, Denary, and Hexadecimal\n* Denary (Base 10): Uses digits $0$ to $9$ with headings $10^{0}, 10^{1}, 10^{2}$, etc.\n* Binary (Base 2): Uses digits $0$ and $1$ with headings $2^{0}, 2^{1}, 2^{2}$, etc. A typical 8-bit heading sequence is $128, 64, 32, 16, 8, 4, 2, 1$.\n* Hexadecimal (Base 16): Uses digits $0$-$9$ and letters $A$-$F$ (where $A=10, B=11, C=12, D=13, E=14, F=15$). One hex digit is equivalent to four binary digits ($2^{4} = 16$).\n\n### Conversion Methods\n* Binary to Denary: Add the column values where a $1$ appears.\n* Denary to Binary Method 1: Successive subtraction of powers of 2 (subtract largest possible power of 2 until 0 is reached).\n* Denary to Binary Method 2: Successive division by 2; the remainders read in reverse order (bottom to top) form the binary number.\n* Binary to Hexadecimal: Split the binary number into groups of 4 bits starting from the right. Convert each group using the 4-bit code table.\n* Denary to Hexadecimal: Successive division by 16. The remainders recorded in reverse order form the hex value.\n\n### 1.1.3 Uses of Hexadecimal\n* Error Codes: Hex values refer to memory locations of errors, automatically generated by the system.\n* MAC Addresses: Media Access Control uniquely identifies a network interface card (NIC). Format: $NN-NN-NN-DD-DD-DD$; first half is manufacturer code, second half is serial number.\n* IPv6 Addresses: 128-bit addresses broken into 16-bit chunks, represented in hex (e.g., $a8fb:7a88:fff0:0fff:3d21:2085:66fb:f0fa$).\n* HTML Colour Codes: Represented as #RRGGBB. Each primary colour (Red, Green, Blue) has 256 possible intensity values ($00$ to $FF$), allowing for $16,777,216$ total colours.\n\n### 1.1.4 Binary Addition\n* Rules:\n * $0 + 0 = 0$\n * $0 + 1 = 1$\n * $1 + 0 = 1$\n * $1 + 1 = 0$ (carry $1$)\n * $1 + 1 + 1 = 1$ (carry $1$)\n* Overflow Error: Occurs when an addition generates a 9th bit in an 8-bit system. It indicates the result is too big for the allocated word size.\n\n### 1.1.5 Logical Binary Shifts\n* Function: Shifting bits left or right in a register.\n* Left Shift: Equivalent to multiplying by 2 for each place shifted. Shifting 4 places left multiplies by $2^{4} = 16$.\n* Right Shift: Equivalent to dividing by 2 for each place shifted.\n* Errors: If a $1$ is shifted out of the register (left or right), bits are lost and the result becomes mathematically incorrect.\n\n### 1.1.6 Two’s Complement\n* Purpose: To represent negative integers in binary.\n* Format: The most significant bit (left-most) represents a negative value (e.g., $-128$ for an 8-bit register).\n* Range: $-128$ ($10000000$) to $+127$ ($01111111$).\n* Conversion (Negative Denary to Binary): Write as a positive binary number, invert all bits ($1$ to $0$, $0$ to $1$), and add 1 to the result.\n\n# DATA TRANSMISSION\n\n## 2.1 Methods of Transmission\n\n### 2.1.1 Data Packets\n* Structure:\n * Header: Source IP, Destination IP, sequence number, packet size.\n * Payload: The actual data (~64 KiB).\n * Trailer: Method to identify the end of the packet and error checking (e.g., Cyclic Redundancy Check).\n* Packet Switching: Messages are broken into packets and sent independently along available routes. Routers determine paths. Packets are reassembled at the destination using sequence numbers.\n\n### 2.1.2 Transmission Modes\n* Simplex: Data in one direction only (e.g., computer to printer).\n* Half-Duplex: Data in both directions, but not at the same time (e.g., walkie-talkie).\n* Full-Duplex: Data in both directions simultaneously (e.g., broadband).\n* Serial: Data sent one bit at a time over a single wire. Reliable for long distances.\n* Parallel: Several bits sent at once over multiple wires. Fast over short distances, but suffers from Skewing (bits arrive out of sync) over long distances.\n\n### 2.1.3 Universal Serial Bus (USB)\n* Type: Serial data transmission using a four-wire shielded cable (2 for power, 2 for data).\n* Benefits: Automatically detects devices, industry standard, backward compatible, supplies power.\n* Drawbacks: Limited cable length (5m), potentially slower than Ethernet.\n* USB-C: 24-pin symmetrical connector, supports 100 watts and 10 Gbps speeds.\n\n## 2.2 Error Detection\n* Parity Check: Uses a parity bit (most significant bit). Even Parity ensures an even number of $1$s; Odd Parity ensures an odd number.\n* Parity Block: Horizontal and vertical parity checks allow the exact bit error to be located (the intersection of incorrect row/column).\n* Checksum: Value calculated using an algorithm at the sender and recalculated at the receiver. If they don't match, an error occurred.\n* Echo Check: Data is sent back to the sender for comparison. Unreliable as the error could occur during the echo.\n* ARQ (Automatic Repeat Request): Uses Acknowledgements (Positive/Negative) and Timeouts. If no acknowledgement is received within a set time, data is re-sent.\n* Check Digit: Final digit in a code (e.g., ISBN-13, Modulo-11) used to identify manual data entry errors or transposition errors.\n\n## 2.3 Encryption\n* Plaintext: Original data before encryption.\n* Ciphertext: Encrypted data produced by an algorithm.\n* Symmetric Encryption: Uses a single key for both encryption and decryption.\n* Asymmetric Encryption: Uses a Public Key (available to all) and a Private Key (known only to the user). Information encrypted with a public key can only be decrypted with the matching private key.\n\n# HARDWARE\n\n## 3.1 Computer Architecture\n\n### 3.1.2 Von Neumann Model\n* Concept: Data and programs are stored in memory. The CPU accesses memory directly.\n* ALU (Arithmetic Logic Unit): Performs calculations ($, +, -, shift$) and logic operations (AND, OR).\n* CU (Control Unit): Manages instruction flow and synchronisation via the system clock.\n* Registers:\n * MAR (Memory Address Register): Stores address of location being read/written.\n * MDR (Memory Data Register): Stores data read from or written to memory.\n * PC (Program Counter): Stores address of the next instruction.\n * CIR (Current Instruction Register): Stores the current instruction being decoded/executed.\n * ACC (Accumulator): Stores results of ALU calculations.\n\n### 3.1.3 Performance Factors\n* Buses: Address Bus (unidirectional), Data Bus (bidirectional), Control Bus (bidirectional).\n* Clock Speed: Measured in GHz; higher speed means more cycles per second.\n* Cores: Multiple cores (Dual, Quad) allow simultaneous instruction processing.\n* Cache: Small, high-speed RAM inside the CPU for frequently used data.\n\n## 3.3 Data Storage\n* Primary Memory: RAM (volatile, read/write) and ROM (non-volatile, read-only, stores BIOS).\n* Secondary Storage: Hard Disk Drive (HDD - magnetic), Solid State Drive (SSD - flash memory), Optical (CD/DVD/Blu-ray).\n* Virtual Memory: Uses swap space on HDD/SSD to extend physical RAM. Can lead to Disk Thrashing (excessive data swapping).\n* Cloud Storage: Storing data on remote servers. Benefits include accessibility; drawbacks include reliance on internet connection and security risks.\n\n# SOFTWARE\n\n## 4.1 Software Types\n* System Software: Manages hardware (OS, Device Drivers, Utilities like Anti-virus and Defragmentation).\n* Application Software: Tasks for the user (Spreadsheets, Word Processors, Databases, Video Editors).\n\n### Operating System (OS) Functions\n* HCI: Provides CLI (Command Line) or GUI (Graphical User Interface).\n* Memory Management: Allocates RAM and manages Virtual Memory.\n* Security: Manages user accounts, passwords, and firewalls.\n* Hardware Management: Uses device drivers to communicate with peripherals.\n* Multitasking: Allocates CPU time to multiple processes.\n* Interrupts: Signals from hardware/software requesting CPU attention. Handled by an Interrupt Service Routine (ISR).\n\n## 4.2 Programming Languages\n* High-Level (HLL): Problem-oriented, portable, easier to read/debug (e.g., Python, Java).\n* Low-Level (LLL): Hardware-specific. Includes Machine Code ($1$s and $0$s) and Assembly Language (uses mnemonics).\n* Translators:\n * Compiler: Translates whole HLL program into machine code once. Fast execution.\n * Interpreter: Translates and executes HLL program line-by-line. Easier debugging.\n * Assembler: Translates assembly language into machine code.\n\n# CYBER SECURITY\n\n## 5.3 Threats and Solutions\n* Brute Force Attack: Trial and error to crack passwords.\n* Data Interception: Packet sniffing or Wardriving.\n* DDoS Attack: Flooding a server with traffic from multiple sources to make it unavailable.\n* Malware: Viruses (replicate with host), Worms (self-replicate), Trojans (disguised), Spyware (monitors activity), Adware, Ransomware (encrypts data for money).\n* Phishing: Emails tricking users into giving data.\n* Pharming: Redirecting users to fake sites via DNS poisoning.\n* Social Engineering: Manipulating human emotions (fear, curiosity) to break security.\n* Solutions: Firewalls, Proxy Servers, SSL/TLS (encryption protocols), 2-Step Verification, Biometrics, and strong access levels.