Differential Amplifiers – Detailed Study Notes

Single-Ended vs. Differential Signals

• Single-ended: referenced to a fixed node (usually ground)

  • Representation: V{SE}(t)=V0\cos\omega t+V_{CM}

• Differential: measured between two nodes that swing equally and oppositely around a common-mode (CM) level

  • Representation: V{diff}(t)=VX-VY=2V0\cos\omega t

  • With single-ended amplitude V0, single-ended pp swing = 2V0, differential pp swing = 4V_0

• CM level = dc bias around which both phases move; must see equal impedances to ground for “true” differential behaviour

• Typical benefit: with a 1-V supply one can still obtain ≈1.6-V differential pp swing

Key Advantages of Differential Operation

• Common-Mode Noise Rejection (CMR)

  • Capacitive coupling from neighbouring aggressors (e.g., clock lines) appears as equal disturbance on both phases and cancels in the subtraction

  • Shielding can be combined with differential routing; twisted-pair routing equalises coupling asymmetries

• Supply noise rejection

  • Single-ended common-source (CS) stage: \Delta V{DD}\rightarrow \Delta V{out} directly

  • Differential pair: equal shifts at both drains, VX-VY unchanged

• Larger allowable swings

  • CS: max swing ≈ V{DD}-V{GS}+V_{TH} (one overdrive from rail)

  • Differential: single-ended swing V{DD}-(V{GS}-V{TH}), differential swing 2[V{DD}-(V{GS}-V{TH})]

• Higher linearity, simpler biasing, modest area penalty (~2× devices)

Basic Differential Pair Topology

• Two matched transistors share tail current I_{SS} implemented by a current source (or degenerated by a resistor)

• Resistive loads R{D1}=R{D2}=R_D provide voltage conversion

• Bias conditions (equilibrium): I{D1}=I{D2}=I{SS}/2, V{out,CM}=V{DD}-RD\frac{I_{SS}}{2}

• Differential input \Delta V{in}=V{in1}-V_{in2} steers the tail current

Qualitative Large-Signal Behaviour

• \Delta V{in}\ll0 → M1 off, M2 carries I{SS}

  • V{out1}=V{DD}, V{out2}=V{DD}-RDI{SS}

• \Delta V_{in}=0 → current splits equally; outputs sit at CM level

• \Delta V_{in}\gg0 → opposite condition; current “hogs” into M1

• Output transfer characteristic for V{out1}-V{out2} is odd-symmetrical, maximum slope at equilibrium

Common-Mode Input Limits

Allowable CM range:
V{GS1}+(V{GS3}-V{TH3})\le V{in,CM}\le \min\Big(V{DD}-\frac{RDI{SS}}{2}+V{TH},\;V_{DD}\Big)

• Lower bound: both input devices must be on + tail source in saturation

• Upper bound: avoid triode operation at outputs

Maximum Output Swing (Large Gain Assumption)

• Each side: V{out,min}\approx V{in,CM}-V{TH}, V{out,max}=V_{DD}

• Single-ended pp swing =V{DD}-\big(V{GS1}-V{TH1}\big)-\big(V{GS3}-V_{TH3}\big)

• Differential pp swing ≈ twice the above

Quantitative Large-Signal Formulas (Square-Law, \lambda=0)

• Relationship between input difference and drain current difference:
  \Delta ID=I{D1}-I{D2}=\sqrt{\munC{ox}\frac{W}{L}I{SS}}\,\Delta V{in}\Bigg[1-\frac{\munC{ox}(W/L)}{4I{SS}}\Delta V_{in}^2\Bigg]^{1/2}

• Cut-off (one side off):
  |\Delta V{in,1}|=\sqrt{\frac{2I{SS}}{\munC{ox}(W/L)}}=\sqrt{2}\,V_{OV(eq)}

• Small-signal transconductance at equilibrium:
  Gm(\text{diff})=\sqrt{\munC{ox}\frac{W}{L}I{SS}}=g_m

• Small-signal differential gain (resistive load):
  |Av|=gmR_D

Intuitive Gm & Linearity Trends

• Gm maximal at \Delta V{in}=0, falls to 0 at cutoff

• Larger I{SS} → higher Gm & wider linear range; larger W/L increases G_m but narrows range

• Degeneration (source resistor RS) widens linear input range by \pm RSI{SS} while reducing gain to |Av|=RD/(gm^{-1}+R_S)

Half-Circuit (Virtual Ground) Concept

• For fully differential small-signal excitation, node P is an ac ground because equal/opposite input swings cause equal source currents → no small-signal voltage change at tail

• Each half behaves as a CS stage: differential gain again =gmRD

• With channel-length modulation: |Av|=gm(RD\parallel rO)

Common-Mode Response & CMRR

• Finite tail impedance R{SS} gives common-mode gain: A{v,CM}=\frac{-RD/2}{R{SS}+1/(2g_m)}

• Mismatch (e.g., \Delta RD or \Delta gm) converts CM variations to differential error:
  A{CM\rightarrow DM}=\frac{-\Delta gm\,RD}{(g{m1}+g{m2})R{SS}+1}

• CMRR definition:
  \text{CMRR}=\left|\dfrac{A{DM}}{A{CM\rightarrow DM}}\right|\approx\dfrac{2gm^2R{SS}}{\Delta gm} (for gmR_{SS}\gg1)

• High-frequency CM disturbances are worsened by tail capacitance C_{SS}

• Body-effect mismatch can still cause CM→DM conversion even with ideal tail source

Differential Pair with Degeneration (Split Tail)

• Splitting I{SS} allows large RS without extra headroom; no dc drop across resistors at equilibrium → maintains swing

Differential Pair with MOS Loads

1. Diode-connected PMOS loads (Fig. 4.37a)

   • Small-signal gain Av\approx-\dfrac{g{mN}}{g{mP}}\approx-\sqrt{\dfrac{\mun(W/L)N}{\mup(W/L)_P}}

   • Consume |V{GS}-V{TH}| headroom each

2. PMOS current-source loads (Fig. 4.37b)

   • Av\approx-g{mN}(r{oN}\parallel r{oP})

   • Gain limited (~5–10 in nano-CMOS)

3. Adding helper current sources (Fig. 4.39) lowers PMOS bias current, boosting gain without extra headroom; resistive loads + PMOS mirrors combine high swing with moderate gain

Cascode Differential Pair (Fig. 4.40)

• Cascoding NMOS & PMOS increases output impedance dramatically:
  |Av|\approx g{m1}\big[(g{m3}r{o3}r{o1})\parallel(g{m5}r{o5}r{o7})\big]

• Trades swing and headroom for gain; requires bias voltages V{b1},V{b2},V_{b3}

Gilbert Cell (Four-Quadrant Multiplier / VGA)

• Built by stacking two input pairs on a differential current-steering pair

• Signal pair (M1–M4) steers current to loads; control pair (M5–M6) directs tail current between upper pairs

• Output: V{out}=RD[(I{D1}+I{D4})-(I{D2}+I{D3})]

• Differential gain proportional to control voltage; varies continuously from +gmRD through 0 to -gmRD

• Acts as analog multiplier: V{out}=\alpha\,V{in}\,V_{cont} (first-order term)

• Requires ≥ one extra overdrive of headroom for stacked topology

• Alternative form: input pair at bottom, control pair on top (Fig. 4.43)

Design Trade-Offs & Practical Notes

• Gain vs. Linearity: larger I_{SS} or degeneration improves linearity; larger W/L boosts gain but worsens linearity window

• Headroom budgeting critical in low-VDD designs; diode loads & cascoding eat voltage

• Nanometer CMOS: \lambda large → intrinsic gain small; cascoding or gain-boost techniques necessary

• Output CM regulation circuits (not covered here) needed for fully differential high-gain op-amps

Representative Example Results

• Example 4.1 (Routing): twisted-pair geometry can null both aggressor & victim differential couplings

• Example 4.2: small-signal gain vs. V{in,CM} rises after V{TH}, plateaus once tail in saturation, falls when inputs enter triode

• Example 4.3: differential pair offers pp swing of 2V{DD}-4V{D,sat} vs. CS stage’s V{DD}-V{D,sat}

• Example 4.4: increasing W/L shrinks linear range; increasing I_{SS} widens it and raises current swing

• Example 4.5 (Offset): dc imbalance equal to half-cutoff voltage biases one side to 83 % of I{SS}, reduces Gm by ≈20 %

• Example 4.9: 50-mV CM error with 500-Ω tail resistor drops output CM by ≈97 mV, pushing inputs toward triode

• Example 4.10: CM→DM conversion rises with frequency (tail capacitance), proportional to 1/\omega reduction in impedance

Ethical & Practical Implications

• Differential signalling increases robustness but doubles device count & routing width; area/power trade must be justified by noise immunity

• Poor CMRR can corrupt precision analog paths; meticulous matching, symmetric layout, and high-impedance current sources mandatory

• VGA/Gilbert cell used in AGC loops; linearity and temperature stability crucial to avoid distortion & gain error