EEE131 Semiconductor Devices: Metal-Oxide-Semiconductor (MOS) Structures Notes

Introduction to Metal-Oxide-Semiconductor (MOS) Structures

  • The MOS structure is recognized as the heart of the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

  • The EEE131 Semiconductor Devices course materials are presented by TS DR Nur Zatil Ismah Hashim from Universiti Sains Malaysia (USM).

Physical Components of the Two-Terminal MOS Structure

  • Metal Plate:

    • The top plate may consist of aluminum (AlAl) or other types of metal.

    • It frequently consists of high-conductivity polycrystalline silicon.

    • Regardless of the specific material used (metal or poly-silicon), the term "metal" is standard academic terminology for this component.

  • Insulator Properties:

    • toxt_{ox} represents the physical thickness of the oxide layer.

    • ϵox\epsilon_{ox} represents the permittivity of the oxide material.

  • Charge and Electric Field:

    • A parallel-plate capacitor model is used to describe the electric field (EE-field) and conductor charges.

    • An insulator separates the plates, and an EE-field is induced between them when a voltage is applied.

    • The prime symbol (′') is used throughout the notation to indicate a value "per unit area."

Operational Modes of the MOS Capacitor (P-type Substrate)

Accumulation

  • Condition: Applying a negative voltage (−V-V) to the metal gate.

  • Mechanism: Majority carrier holes move toward the oxide-semiconductor interface.

  • Result: A hole accumulation layer forms at the interface. The semiconductor surface appears more p-type than the bulk material.

Depletion

  • Condition: Applying a moderate positive voltage (+V+V) to the metal gate.

  • Mechanism: Positive gate bias induces an electric field that pushes majority carrier holes away from the interface.

  • Result:

    • A negative space charge region is created due to the remaining ionized acceptor atoms (NA−N_A^-).

    • NA−N_A^- corresponds to the negative charge on the bottom "plate" of the MOS system.

    • The induced space charge width is denoted as xdx_d.

Inversion

  • Condition: Applying a large positive voltage (++V++V) to the metal gate.

  • Mechanism: The space charge width reaches a maximum value (xdTx_{dT}).

  • Result:

    • An inversion layer of electrons is created at the oxide-semiconductor interface.

    • The semiconductor surface is effectively inverted from p-type to n-type.

Energy Band Diagrams and Thermal Equilibrium

  • Flat-Band Condition (VG=0V_G = 0):

    • Energy bands in the semiconductor are flat, indicating zero net charge in the semiconductor.

    • The discussion assumes ideal conditions unless stated otherwise.

  • Accumulation (VG=−VEV_G = -VE):

    • The conduction band (ECE_C), valence band (EVE_V), and intrinsic Fermi level (EFiE_{Fi}) edges bend upwards.

    • EVE_V becomes closer to the Fermi level (EFE_F) at the interface than in the bulk.

    • EFE_F remains constant across the semiconductor because the system is in thermal equilibrium and no current flows through the oxide.

  • Depletion (VG=+VEV_G = +VE):

    • ECE_C, EVE_V, and EFiE_{Fi} edges bend downwards.

    • ECE_C and EFiE_{Fi} move closer to EFE_F.

    • A space charge region similar to a PN junction is formed, and its width (xdx_d) increases as +VG+V_G increases.

  • Strong Inversion (VG=++VEV_G = ++VE):

    • Bands bend further downward.

    • ECE_C moves significantly closer to EFE_F, and EFiE_{Fi} crosses over EFE_F.

Mathematical Modeling of the Space Charge Region

  • Bulk Potential (Φfp\Phi_{fp}): Specified as the difference (in Volts) between EFiE_{Fi} and EFE_F.

    • Φfp=Vtln⁡(Nani)\Phi_{fp} = V_t \ln(\frac{N_a}{n_i})

    • Where NaN_a is acceptor doping and nin_i is intrinsic carrier concentration.

  • Surface Potential (Φs\Phi_s):

    • Defined as the difference (in Volts) between EFiE_{Fi} measured in the bulk and EFiE_{Fi} at the surface.

    • It represents the potential difference across the space charge layer and defines the band-bending magnitude.

  • Depletion Layer Thickness (xdx_d):

    • Calculated using the abrupt depletion approximation:

    • xd=2ϵsΦseNAx_d = \sqrt{\frac{2 \epsilon_s \Phi_s}{e N_A}}

    • Where ϵs\epsilon_s is semiconductor permittivity.

  • Maximum Depletion Layer (xdTx_{dT}):

    • Reached at the onset of strong inversion (threshold condition) when Φs=2Φfp\Phi_s = 2\Phi_{fp}.

    • xdT=4ϵsΦfpeNAx_{dT} = \sqrt{\frac{4 \epsilon_s \Phi_{fp}}{e N_A}}

    • At the threshold, the electron concentration at the surface (npn_p) equals the hole concentration in the bulk.

    • Because npn_p is an exponential function of Φs\Phi_s, any slight increase in Φs\Phi_s results in an orders-of-magnitude increase in electron density, meaning xdx_d essentially saturates at xdTx_{dT}.

Example 2.1: Maximum Space Charge Width

  • Inputs: Silicon at T=300 KT = 300\,K, Na=1016 cm−3N_a = 10^{16}\,cm^{-3}, ni=1.5×1010 cm−3n_i = 1.5 \times 10^{10}\,cm^{-3}.

  • Step 1 (Bulk Potential): Φfp=0.0259ln⁡(10161.5×1010)=0.3473 V\Phi_{fp} = 0.0259 \ln(\frac{10^{16}}{1.5 \times 10^{10}}) = 0.3473\,V.

  • Step 2 (Calculation):

    • xdT=[4(11.7)(8.85×10−14)(0.3473)(1.6×10−19)(1016)]1/2x_{dT} = [\frac{4(11.7)(8.85 \times 10^{-14})(0.3473)}{(1.6 \times 10^{-19})(10^{16})}]^{1/2}

    • Result: xdT=0.30×10−4 cm=0.30 μmx_{dT} = 0.30 \times 10^{-4}\,cm = 0.30\,\mu m.

Non-Ideal Effects and Flat-Band Voltage

  • Work Function Difference (Φms\Phi_{ms}):

    • In real devices, Φm≠Φs\Phi_m \neq \Phi_s at VG=0V_G = 0.

    • Φms=Φm′−(χ′+Eg2e+Φfp)\Phi_{ms} = \Phi'_m - (\chi' + \frac{E_g}{2e} + \Phi_{fp}) for p-type.

    • Φm′\Phi'_m: Modified metal work function.

    • χ′\chi': Modified electron affinity.

  • Oxide Charges:

    • An assumption of zero charge in the oxide is rarely valid.

    • Positive fixed charge (Qss′Q'_{ss}) typically exists near the oxide-semiconductor interface.

    • Origin: Broken or dangling covalent bonds from silicon atoms during thermal oxidation or interrupted silicon reaction.

    • Charge density is affected by oxidizing ambient, temperature, and annealing in argon or nitrogen.

  • Flat-Band Voltage (VFBV_{FB}):

    • The voltage required to negate band-bending and induce zero EE-field at the interface.

    • VFB=Φms−Qss′CoxV_{FB} = \Phi_{ms} - \frac{Q'_{ss}}{C_{ox}}

Example 2.3: Flat-Band Voltage

  • Inputs: P-type substrate, tox=20 nmt_{ox} = 20\,nm, Φms=−1.1 V\Phi_{ms} = -1.1\,V, Qss′=5×1010 electronic charges/cm2Q'_{ss} = 5 \times 10^{10}\,electronic\,charges/cm^2.

  • Calculations:

    1. Cox=(3.9)(8.85×10−14)20×10−7=1.726×10−7 F/cm2C_{ox} = \frac{(3.9)(8.85 \times 10^{-14})}{20 \times 10^{-7}} = 1.726 \times 10^{-7}\,F/cm^2.

    2. Qss′=(5×1010)(1.6×10−19)=8×10−9 C/cm2Q'_{ss} = (5 \times 10^{10})(1.6 \times 10^{-19}) = 8 \times 10^{-9}\,C/cm^2.

    3. VFB=−1.1−8×10−91.726×10−7V_{FB} = -1.1 - \frac{8 \times 10^{-9}}{1.726 \times 10^{-7}}.

  • Result: VFB=−1.15 VV_{FB} = -1.15\,V.

Threshold Voltage (VTV_T)

  • Definition: The gate voltage required to reach the threshold inversion point (Φs=2Φfp\Phi_s = 2\Phi_{fp} for P-type).

  • Charge Conservation: Qm′+Qss′+QSD′(max)=0Q'_m + Q'_{ss} + Q'_{SD}(max) = 0

    • QSD′(max)=−eNaxdTQ'_{SD}(max) = -e N_a x_{dT}

  • Formula for VTNV_{TN} (P-type Substrate):

    • VTN=[∣QSD′(max)∣−Qss′Cox]+Φms+2ΦfpV_{TN} = [\frac{|Q'_{SD}(max)| - Q'_{ss}}{C_{ox}}] + \Phi_{ms} + 2\Phi_{fp}

  • Enhancement vs. Depletion Mode:

    • A negative VTNV_{TN} for a P-type substrate implies a depletion mode device (negative voltage needed to zero the inversion charge).

    • Enhancement mode (positive VTNV_{TN}) requires heavier doping.

Capacitance-Voltage (C-V) Characteristics

  • Measurement: Capacitance is a small-signal (AC) parameter measured by superimposing a small AC voltage on a DC gate bias (VGV_G).

  • Ideal C-V Regions (P-type):

    1. Accumulation: Negative bias causes hole accumulation. Differential change in voltage changes the hole accumulation charge. Capacitance is high and equals Cox′C'_{ox}.

    2. Depletion: Positive bias increases space charge width xdx_d. Capacitance decreases as xdx_d increases.

      • 1C′(depl)=1Cox′+1Csd′\frac{1}{C'(depl)} = \frac{1}{C'_{ox}} + \frac{1}{C'_{sd}}

    3. Inversion: Large positive bias. Under low frequency, capacitance returns to Cox′C'_{ox} because the inversion layer charge density changes with the AC signal.

  • Minimum Capacitance (Cmin′C'_{min}): Occurs at the threshold inversion point.

    • Cmin′=ϵoxtox+(ϵoxϵs)xdTC'_{min} = \frac{\epsilon_{ox}}{t_{ox} + (\frac{\epsilon_{ox}}{\epsilon_s}) x_{dT}}

  • Flat-Band Capacitance (CFB′C'_{FB}):

    • CFB′=ϵoxtox+(ϵoxϵs)VtϵseNaC'_{FB} = \frac{\epsilon_{ox}}{t_{ox} + (\frac{\epsilon_{ox}}{\epsilon_s}) \sqrt{\frac{V_t \epsilon_s}{e N_a}}}

Frequency and Interface Charge Effects

  • Frequency Effects:

    • In inversion, minority carrier (electron) concentration cannot change instantaneously.

    • Low Frequency: Inversion layer responds to AC signal; C′C' remains high.

    • High Frequency: Inversion layer cannot respond; change in charge occurs at the edge of the depletion region. C′C' remains at a minimum constant value (Cmin′C'_{min}) even in inversion.

  • Fixed Oxide Charge:

    • Causes a parallel shift in the C-V curve (typically to the left for positive charge).

    • Shape remains the same as the ideal curve.

  • Interface Charge (Interface States):

    • Energy states within the band gap due to the termination of the lattice periodic structure.

    • These states exchange charge with the semiconductor depending on the Fermi level position.

    • Result: The C-V curve becomes "smeared out" because the charge of interface states varies with applied gate voltage.