Lecture Notes on NMOS, CMOS, & BiCMOS Circuits (Digital Electronics)

Lecture Objectives

• Basic NMOS Circuits
• NMOS Inverter Analysis
• NMOS Logic Gates
• CMOS Circuits
• CMOS Inverter Analysis
• CMOS Logic Gates
• BiCMOS Circuits

NMOS Inverter with Resistive Load

Circuit Operation

• Low Input Voltage: If $v<em>{i} < V</em>{t}$, the NMOS is OFF, thus $i<em>{D} = 0$, leading to $v</em>{o} = V_{DD}$.
• High Input Voltage: If $v<em>{i} > V</em>{t}$, the NMOS is ON, resulting in a non-zero drain current $i<em>{D}$. The output voltage is given by: $v</em>{o} = V<em>{DD} - i</em>{D}R_{D}$

Voltage Transfer Characteristics (VTC)

1. Thresholds:
   • $V_{OO}$: Output voltage when inverter input is low.
   • $V_{IM}$: Input voltage at which the transition from low to high occurs.
2. Formula relating $R<em>{L}$ and $v</em>{i}$ to output $ ext{V}{O}$ through load resistance $R</em>{L}$.
3. Small signal model can be applied for detailed inverter behavior.

Refreshing MOS Transistor Theory

• Regions of Operation:
  • Cut-off: $v<em>{GS} ext{ (gate to source)} ext{ is less than } V</em>{t}$
  • Linear: $V<em>{DS} < (V</em>{GS} - V_{t})$
  • Saturation: $V<em>{DS} ext{ is greater than } (V</em>{GS} - V_{t})$

Important Parameters

• Transconductance $g_{m}$
• Output Resistance $r_{o}$
• Drain Current $i_{D}$
  • Linear region:
    $i<em>{D} = k</em>{n}(v<em>{GS} - V</em>{t})v_{DS}$
  • Saturation region:
    $i<em>{D} = \frac{k</em>{n}}{2}(v<em>{GS} - V</em>{t})^2(1 + \frac{\beta V_{DS}}{L})$

NMOS Inverter Voltage Transfer Characteristics

Finding $V_{OO}$

• Assume input low ($v<em>{i} < V</em>{t}$) implies $Q$ is OFF:
  $V<em>{OO} = V</em>{DD}$
• Setting $V<em>{i} = V</em>{OO}$ gives:
  $v<em>{G} = v</em>{i} = V_{DD}$ leading to the following rearranged relationships for analysis.

Static and Dynamic Power Dissipation

Static Power Dissipation

• For 50% duty cycle digital signals:
  $P<em>{stat} = V</em>{DD} imes i_{D}$
• Average voltage during low circuit state:
  $P<em>{stat} ext{ when output is low} = \frac{V</em>{DD}}{2} imes (V<em>{DD} - V</em>{OO})$

Dynamic Power Dissipation

• At transitions:
  $P<em>{d} ext{ during charging} = V</em>{DD} imes (i(t))$
• Energy stored in capacitor ($C<em>{L}$): $E</em>{C} = \frac{1}{2}C<em>{L}V</em>{DD}^2$

Propagation Delay

• Asses delays from PUN/PDN switching by defining the signal characteristics and load capacitance interactions:
  $t<em>{p} = C</em>{L} \frac{V<em>{DD}}{2i</em>{D}}$

CMOS Inverter Design Guidelines

Capacitive Load Calculations

• Total capacitance includes:
  • Gate capacitance $(C_{G})$ from the device characteristics
  • Parasitic capacitances $(C_{P})$, including junction and side-wall capacitance.

Timing and Power Characteristics

• Using standard formulas, capacity, current, and voltage ratios dictate the operational speed and efficiency of CMOS inverters.

Example Problem Solving Framework

1. Construct gate logic using NMOS and PMOS networks respecting the relationship laws between inputs and outputs.
2. Analyze timing characteristics based on electrical parameters.
3. Apply this knowledge to append circuit designs ensuring effective signal dissipation and propagation times.

Conclusion

• The operational principles of NMOS, CMOS, and BiCMOS circuits are foundational in Digital Electronics as addressed in this lecture.