Machine code

INTRODUCTION

• Construction of CPU focused on the Datapath.
• Instructions manipulate data via the Datapath.
• Control logic manages instruction flow based on opcodes.

ARM CPU ARCHITECTURE

• Registers in the center; paths to ALU via direct and barrel shifter routes.
• Status Register (flags) reflects ALU outputs.

OPCODES

• Unique binary numbers assigned to each instruction.
• Instructions for 6502 coded as 8-bit bytes.
• Logical simplifications in opcode assignment are crucial.

INSTRUCTION ENCODING

• Encodes address mode & operation separately (e.g., 6502 encoding).
• Defines bits for operation (aaa) and addressing mode (bbb).
• Instruction example: LDA encoded using specific bit patterns.

DECODING INSTRUCTIONS

• Enables simpler construction of decode logic.
• Three bits for memory access, three bits for ALU logic.

STATUS FLAGS

• CPU flags indicate operation results (Negative, Zero, Overflow, Carry).
• Flags generated based on ALU operations.

BRANCHING

• Conditional jumps based on status flags.
• Instruction forms dictate flag comparisons for branch decisions.

FETCH-DECODE-EXECUTE CYCLE

• Sequential process ensures instructions are fetched, decoded, and executed per clock cycle.
• Each instruction takes at least three cycles (fetch, decode, execute).