Machine Language, Control Units, and Pipelined Execution in Computer Architecture

Machine Language and Initial Memory State

• Hardware Components and Addressing:

  • ALU (Arithmetic Logic Unit): Responsible for performing computations.
  • General Purpose (GP) Registers: Identified as $A$, $B$, $C$, and $D$.
  • I/O Unit Addresses: Specific memory-mapped inputs/outputs include #0, #128, #255, and #127.

• Initial Program (P1) Machine Code and Assembly Mapping:

  • Address 1: $11000000 \, 00001100$ translates to load #12, A.
  • Address 2: $11000001 \, 00001101$ translates to load #13, B.
  • Address 3: $00000001 \, 10000000$ translates to add A, B, C.
  • Address 4: $11011000 \, 00001110$ translates to store C, #14.

• Initial Memory State (Data Storage):

  • Memory location #11: Value $12$ ($00001100$).
  • Memory location #12: Value $6$ ($00000110$).
  • Memory location #13: Value $2$ ($00000010$).
  • Memory location #14: Value $3$ ($00000011$).

The Control Unit (CU) and Primary Registers

• Program Counter (PC):

  • Holds the memory address from which the next instruction will be loaded.
  • It is updated only after the execution of an instruction has been finalized.

• Instruction Register (IR):

  • Loads the current instruction from the memory address indicated by the PC.
  • Holds the instruction during its entire execution cycle.
  • The CU utilizes IR contents to:
    • Decode the op-code to determine the specific instruction.
    • Determine operands and the source of their values.
    • Retrieve actual values.
    • Allocate processor resources required for execution.
  • Structure: In this example, an instruction is $2\,bytes$ ($16\,bits$); therefore, the IR consists of $2 \times 8\text{-bit}$ registers. For more advanced pipelined processors, the IR is a complex structure.

• Processor Status Word (PSW):

  • Records results from operations performed by the last instruction.
  • Registers specific flags such as:
    • Zero
    • Negative
    • Positive
    • Integer
    • Fractional
    • Overflow
    • Carry

The Fetch-Execute Loop

• 1. Instruction Fetch:

  • A special type of software-automated load that occurs for every instruction.
  • The PC acts as the source, and the IR acts as the destination (Logic: load PC IR).
  • Loads the contents of the memory address found in PC into the IR.

• 2. Instruction Decoding:

  • The instruction in the IR is analyzed for:
    • Mode: Execution mode.
    • Op-code: The operation to be performed.
    • Operands: Source(s) and destination(s).
    • Operation: The specific logic required.
    • Immediate Values: Numerical values embedded in the instruction.

• 3. Instruction Execution:

  • Arithmetic Instructions: Executed using the ALU and registers.
  • Memory-Access Instructions: Executed using dedicated memory-access hardware.

• Timing of Updates:

  • The PSW is updated immediately after the execution phase.
  • The PC is updated after the execution phase to point to the next instruction.

Program Execution Trace: Program P1

• Step 1 (Starting at Address #200):

  • Fetch: Load load #12, A into IR; increment PC to #202.
  • Decode: Decodes instruction as loading the value from memory address #12 into General Purpose register $A$.
  • Execute: Uses memory-access hardware to complete the load.

• Step 2 (Starting at Address #202):

  • Fetch: Load load #13, B into IR; increment PC to #204.
  • Decode: Decodes instruction as loading the value from memory address #13 into General Purpose register $B$.
  • Execute: Uses memory-access hardware to complete the load.

• Step 3 (Starting at Address #204):

  • Fetch: Load add A, B, C into IR; increment PC to #206.
  • Decode: Decodes instruction as adding values in registers $A$ and $B$ and storing the result in $C$.
  • Execute: Uses ALU and registers.

• Step 4 (Starting at Address #206):

  • Fetch: Load store C, #14 into IR; increment PC to #208.
  • Decode: Decodes instruction as storing the value in register $C$ into memory address #14.
  • Execute: Uses memory-access hardware.

Branch Instructions

While arithmetic and memory-access instructions are typically sequential, branch instructions allow non-linear program flow.

• Directional Types:

  • Forward Branch: Jumps to an instruction at a higher memory address.
  • Backward Branch: Jumps to an instruction at a lower memory address.

• Generic Format: branch_mnemonic #target

  • This forces the PC to take the value #target instead of the standard increment.
  • Technically categorized as memory-access instructions, but they access code storage instead of data storage.

• Unconditional Branch:

  • Assembler Syntax: jump #target
  • Always jumps to #target, which can be an immediate memory address (e.g., jump #12) or a memory address stored in a register (e.g., jump #D).

• Conditional Branch:

  • Example: jumpz #target (Jump if Zero).
  • Mechanism: If the previous arithmetic result was $0$, the instruction jumps to #target. If not, it continues to the next sequential line.
  • The CU checks the ZERO bit in the PSW (e.g., if $Result = 0$, then $ZERO = 1$; if $Result \neq 0$, then $ZERO = 0$).
  • Other variants: jumpneg (negative), jumppos (positive), jumpint (integer), jumpfrac (fractional), jumpcarry (carry).

Modern Pipelined Execution

• Limitation of Sequential Execution: Standard sequential processing is simple but slow, representing early digital computing evolution.

• Pipelining Concept: Modern processors use pipelined execution to increase instruction throughput.

• Four-Stage Instruction Life-Cycle Model:

  1. Fetch: Load instruction from PC address to IR; increment PC.
  2. Decode: Analyze instruction in IR.
  3. Execute: Perform the operation (e.g., in ALU, read contents of registers $A$ and $B$ and add them).
  4. Write-back: Record the result back into the destination register (e.g., Register $C$).

• Comparison of Non-Pipelined vs. Pipelined Performance:

  • Processor Cycle: The time spent to complete all stages of one instruction. This is distinct from the clock rate.
  • Non-Pipelined (Single-cycle) Scenario:
    • Works on one instruction at a time.
    • Assume instruction duration = $4\,ns$ (divided into four $1\,ns$ stages).
    • Program P1 ($4\,instructions$) takes $16\,ns$.
  • Pipelined Scenario:
    • Works on $4\,instructions$ simultaneously during a single processor cycle.
    • Theory: Program execution should be $4 \times$ faster at the same clock frequency.
    • Practice: Program P1 execution time is actually $7\,ns$ (not $4\,ns$).
    • Efficiency Factors: The $7\,ns$ result is due to the time required to fill the pipeline initially and the pipeline becoming empty at the end. Maximum efficiency (4 instructions per cycle) is only reached once the pipeline is full and remains full.

Reference and Resources

• Primary Source: Jon Stokes (2006). Inside the machine: an illustrated introduction to microprocessors and computer architecture. No Starch Press – ARS technical library. ISBN-13: $978-1-59327-668-3$ (Chapters 1 and 2).

Questions & Discussion

• The document concludes with a slide for "Questions". No specific dialogue or audience interaction was recorded in the transcript provided.