ARCHORG PREFI
Memory is the part of the computer that stores data, instructions, and results temporarily or permanently.
Examples:
- RAM
- ROM
- Cache Memory
- Hard Drive / SSD
Types of Memory
Primary Memory - Directly accessed by CPU (Volatile)
Secondary Memory - Stores data permanently (Non-volatile)
Cache Memory - Speeds up CPU operations (Volatile)
ROM - Stores firmware (Non-volatile)
Input/Output (I/O) systems allow a computer to take data in (input) and send data out (output).
Examples:
- Input: Keyboard, Mouse, Scanner
- Output: Monitor, Printer, Speaker
Memory = Data storage
I/O Systems = Data exchange
Memory Hierarchy refers to the structure that organizes computer memory based on speed, cost, and size.
Memory Hierarchy Design
Registers are small, high-speed memory units located in the CPU.
Cache memory is a small, fast memory unit located close to the CPU.
Main memory, also known as RAM (Random Access Memory), is the primary memory of a computer system.
Static RAM: Static RAM stores the binary information in flip flops and information remains valid until power is supplied.
Dynamic RAM: It stores the binary information as a charge on the capacitor.
Secondary storage, such as hard disk drives (HDD) and solid-state drives (SSD) , is a non-volatile memory unit that has a larger storage capacity than main memory.
Magnetic Disks are simply circular plates that are fabricated with either a metal or a plastic or a magnetized material.
Magnetic Tape is simply a magnetic recording device that is covered with a plastic film.
Characteristics of Memory Hierachy
Capacity: It is the global volume of information the memory can store. As we move from top to bottom in the Hierarchy, the capacity increases.
Access Time: It is the time interval between the read/write request and the availability of the data. As we move from top to bottom in the Hierarchy, the access time increases.
Performance: The Memory Hierarch design ensures that frequently accessed data is stored in faster memory to improve system performance.
Cost Per Bit: As we move from bottom to top in the Hierarchy, the cost per bit increases i.e. Internal Memory is costlier than External Memory.
Advantages
Performance: Frequently used data is stored in faster memory (like cache), reducing access time and improving overall system performance.
Cost Efficiency: By combining small, fast memory (like registers and cache) with larger, slower memory (like RAM and HDD), the system achieves a balance between cost and performance. It saves the consumer's price and time.
Optimized Resource Utilization: Combines the benefits of small, fast memory and large, cost-effective storage to maximize system performance.
Efficient Data Management: Frequently accessed data is kept closer to the CPU, while less frequently used data is stored in larger, slower memory, ensuring efficient data handling.
Disadvantages
Complex Design: Managing and coordinating data across different levels of the hierarchy adds complexity to the system's design and operation.
Cost: Faster memory components like registers and cache are expensive, limiting their size and increasing the overall cost of the system.
Latency: Accessing data stored in slower memory (like secondary or tertiary storage) increases the latency and reduces system performance.
Maintenance Overhead: Managing and maintaining different types of memory adds overhead in terms of hardware and software.
Input systems refer to the devices or components that allow users to interact with a computer or other electronic device, providing data or instructions.
Examples include:
- Keyboards: for typing text and commands
- Mice: for navigation and selection
- Touchscreens: for direct interaction with the display
- Sensors: for detecting environmental changes (e.g., temperature, light)
- Microphones: for voice commands or audio input
- Cameras: for capturing images or video
Output systems refer to the devices or components that display or present information to the user, providing results or feedback.
Examples include:
- Monitors: for displaying visual information
- Speakers: for producing sound
- Printers: for printing documents or images
- LED displays: for showing numerical or textual information
- Haptic feedback devices: for providing tactile feedback (e.g., vibrations)
Direct Mapped Cache
Each memory block has only ONE specific cache location
Memory address has 3 parts: Tag, Index, Offset
Index tells exactly which cache line to use
Formula: Cache Line = Block Number MOD Total Cache Lines
Pros: Simple, fast, cheap
Cons:Many conflicts, poor performance
Fully Associative Cache
Memory blocks can go ANYWHERE in cache
Memory address has 2 parts: Tag, Offset
Must check ALL cache lines to find data
Pros: No conflicts, best usage
Cons:Complex, expensive, slow
Set-Associative Cache
Mix of both methods
Cache divided into groups called “sets”
Memory address has 3 parts: Tag, Set Index, Offset
Set Index picks which set to use
Pros: Good balance, fewer conflicts
Cons:More complex than direct mapped
Cache Memory
-Small, high-speed memory near the CPU
-Stores frequently used data
-Boosts processing speed
Cache Replacement Policies
FIFO – Oldest block replaced first
LRU – Least recently used block removed
LFU – Least frequently used
Random – Unpredictable but simple
Write-Through Policy
-Writes go to both cache & main memory
-Ensures consistency
-Slower performance
Write-Back Policy
-Writes only in cache first
-Faster, fewer writes
-Risk: data loss if cache fails
Write-Allocate: load data into cache on write miss
No-Write-Allocate: write directly to memory
Common pairings:
- Write-Back + Write-Allocate
- Write-Through + No-Write-Allocate
Virtual memory management is a crucial aspect of modern operating systems that allows a computer to use more memory than is physically available by utilizing disk space as an extension of RAM.
Paging is a memory management scheme that eliminates the need for contiguous allocation of physical memory and thus eliminates the problems of fitting varying sized memory chunks onto the backing store.
Key Concepts
Pages and Frames: The virtual memory is divided into fixed-size blocks called pages, while physical memory is divided into frames of the same size.
Page Table: A data structure used to map virtual page numbers to physical frame numbers.
Page Fault: Occurs when a program accesses a page that is not currently in physical memory, triggering the operating system to load the page from disk.
Advantages
No External Fragmentation: Since pages are of fixed size, there is no external fragmentation.
Simplified Memory Management: The fixedsize pages simplify the allocation and deallocation of memory.
Efficient Use of Memory: Allows for efficient use of memory by loading only the necessary pages
Disadvantages
Internal Fragmentation: If a process does not use the entire page, the unused space within the page is wasted.
Overhead of Page Tables: Maintaining page tables can consume additional memory and processing time.
Page Fault Overhead: Frequent page faults can lead to performance degradation.
Segmentation is a memory management technique that divides the virtual memory into variable-sized segments based on the logical structure of a program, such as functions, objects, or data structures.
Key Concepts
Segments: Each segment represents a logical unit of the program, such as a function or an array.
Segment Table: A data structure that maps segment numbers to physical addresses and segment lengths.
Segment Fault: Occurs when a program tries to access a segment that is not currently in memory.
Advantages
Logical Organization: Segmentation reflects the logical structure of a program, making it easier to manage.
Reduced Internal Fragmentation: Since segments can vary in size, there is less wasted space compared to fixed-size pages.
Ease of Growing Data Structures: Segments can grow dynamically, accommodating varying sizes of data.
Disadvantages
External Fragmentation: Over time, free memory may become fragmented, making it difficult to allocate large contiguous blocks.
Complex Management: Managing variablesized segments can be more complex than fixed-size pages.
Segment Fault Overhead: Similar to page faults, accessing a non-resident segment incurs overhead.
The Translation Lookaside Buffer (TLB) is a specialized cache used to improve the speed of virtual address translation by storing recent translations of virtual memory addresses to physical memory addresses.
Key Concepts
Cache for Page Table Entries: The TLB stores a limited number of page table entries to speed up address translation.
TLB Hit and Miss: A TLB hit occurs when the required translation is found in the TLB, while a miss requires accessing the page table in memory.
Replacement Policies: TLB entries are managed using various replacement policies (e.g., Least Recently Used, First-In-First-Out).
Advantages
Faster Address Translation: TLB significantly reduces the time taken to translate virtual addresses to physical addresses.
Improved Performance: By minimizing the number of accesses to the page table, the overall performance of the system is enhanced.
Reduced Latency: TLB hits can reduce the latency of memory access, leading to faster program execution.
Disadvantages
Limited Size: The TLB can only store a limited number of entries, which may lead to misses if the working set of pages exceeds its capacity.
Overhead of Management: Maintaining the TLB and handling misses can introduce additional overhead.
Complexity: The implementation of TLBs adds complexity to the memory management unit (MMU)
Computer Bus is a communication system that transfers data between components inside a computer, or between computers.
Three Pillars of the Bus System
Data Bus - carries the actual data being transferred between the processor, memory, ang I/O.
Address Bus - specifies the source or destination of the data on the data bus
Control Bus - carries control and timing signals to manage the flow of information and coordinate the activities of all connected devices
Data and Address Bus Characteristics
Data Bus Width
The width of the data bus determines how many bits can be transferred simultaneously
Address Bus Capacity
The width of the address bus determines the maximum memory capacity the system can address
The Role of the Control Bus
Read/Write Signals - indicate whether the CPU is requesting to read data from or write data to a specific location
Clock Signals - provide synchronization for all components
Interrupt Signals - allow I/O devices to request the CPU’s attention, pausing current operations for urgent tasks
Bus arbitration - is the process of determining which device is granted control of the bus at any given time to prevent conflicts.
Arbitrate
Grant
Release
Request
Centralized - a single bus controller manages all access requests
Decentralized - each device has its own logic to determine success, often using a priority scheme