REVIEW of 331

CMPEN 431 Computer Architecture

  • Spring 2025

  • Jack Sampson (www.cse.psu.edu/~sampson)

  • Alexandar Devic

  • Review Slides Part 1: Chapter 2, "Instructions: Language of the Computer"

Resources for Further Study

  • Reading Materials:

    • MIPS ISA Review, PH, Chapter 2, Appendix A (RISC-V also applicable)

    • MIPS ALU Review, PH, Chapter 3 (RISC-V also applicable)

  • Lecture Slides:

    • For a slower-paced review, refer to Lectures 2-5 from Fall 2016 on CANVAS.

  • Concepts: Review fast-paced slides but feel free to ask questions during class.

  • If unsure about arithmetic from CMPEN 270, review it independently, as class time will focus on advanced topics.

Evaluating Instruction Set Architectures (ISAs)

Design-Time Metrics

  • Feasibility:

    • Can the ISA be implemented?

    • What are the costs associated with design, fabrication, testing, and packaging?

    • What is its power consumption and reliability?

  • Programmability:

    • Ease of compilation must be considered.

Static Metrics

  • Memory footprint:

    • How many bytes does the program occupy?

Dynamic Metrics

  • Execution performance:

    • Number of instructions executed.

    • Bytes fetched by the processor for execution.

    • Clocks required per instruction.

    • Overall execution time is the best metric.

Key Performance Indicator (KPI)

  • CPI (Cycles Per Instruction):

    • Affects: Instruction count and cycle time.

    • Influenced by the instruction set, processor organization, and compilation approaches.

Principles of Machine Design

  1. Instructions & Data Representation:

    • Instructions are encoded as numbers and indistinguishable from data.

  2. Stored Program Concept:

    • Programs can be stored as binary number files, allowing compatibility if ISAs are aligned.

Von Neumann Architecture: Fetch/Execute Cycle

  1. Instruction Fetch: Read from memory using the Program Counter (PC) address.

  2. Decoding: Control unit decodes the instruction and generates signals.

  3. Execution:

    • Reads operands from registers or memory.

    • Executes as directed by control.

  4. Result Storage: Writes back results to registers or memory.

  5. PC Update: Advances to the next instruction address.

RISC vs. CISC

  • RISC (Reduced Instruction Set Computer):

    • Examples: MIPS, SPARC, PowerPC, ARM, RISC-V.

    • Focus: Simple instructions for speed.

  • CISC (Complex Instruction Set Computer):

    • Example: x86 architecture.

    • Goals prioritize design efficiency, smaller implementation sizes and performance.

MIPS Design Principles

Simplicity Favors Regularity

  • Regular designs simplify implementation and reduce costs, promoting performance.

Smaller is Faster

  • Simple ISAs minimize size and power without sacrificing speed.

MIPS Instruction Format & Categories

Instruction Categories:

  • Computational

  • Load/Store

  • Jump and Branch

  • Floating Point Operations

Three Instruction Formats:

  • All instructions are 32 bits.

  • Register File Layout defined.

MIPS Instruction Fields

  • Names given for easier reference, include opcode, source and destination register addresses, and shift amount.

MIPS Organization Overview

  • Processor and Memory: Understand the basic layout of registers and memory addressing.

  • Data Path Flow: Understand how instructions are fetched, decoded, executed, and written back to memory.

MIPS Addressing Modes

  • Different modes for data access: register, base, immediate, PC-relative, pseudo-direct addressing.

MIPS Arithmetic Instructions

  • MIPS Assembly Examples:

    • add $t0, $s1, $s2

    • Instruction format defines the operation with specific registers for source and destination values.

MIPS Procedure Calls & Handling

Execution of a Procedure

  1. Pass arguments using designated registers.

  2. Implement transfer control with jal instruction.

  3. Save return address in $ra for returning to the calling function.

  4. Manage stack for space needed in case of more arguments.

Spilling Registers

  • Handle scenarios where more registers are needed than allocated.

MIPS Memory Access Instructions

  • Data Transfer Instructions: lw and sw help in loading and storing data from/to registers.

  • Memory addressing relies on base register and offset.

Floating Point Handling in MIPS

  • Separate floating point unit with a dedicated register file.

  • Support for IEEE 754 standard for floating-point representation.

Cache Memory and Performance Challenges

  • Understand the importance of the memory hierarchy and its effects on performance.

  • Cache Miss Types: Compulsory, Capacity, and Conflict misses, each with distinct resolutions.

Cache Performance Metrics

  • Assessing cache hit/miss rates and their effects on overall CPU time through AMAT (Average Memory Access Time).

  • Consider the interplay between ideal CPI and memory stalls affecting performance.

Memory Management and Cache Design

  • Implementing cache requires managing how data blocks are accessed, including the use of metadata and mapping functions.

  • Understanding the trade-offs in size, speed, and access patterns is vital for cache efficacy.

Conclusion

  • Recognize the critical balance required in modern architectures to manage performance, memory latency, and branch prediction for optimal operations.

  • Must resolve hazards intelligently to maintain execution flow effectively.