Systems Org

Dram (Dynamic Random-access memory)A stored value represented by a capacitor’s charge state - 1 capacitor - 1 access transistor A capacitor is like a bucket that can store a charge This charge can leak away quickly unless the capacitor’s charge is refreshed This refreshing is performed by the CPU, or by a dedicated memory controller Every bit must be read and written-back 1000s of times/second.

SRAM (Static Random Access Memory) Two cross-coupled inverters store a single bit -Bit maintained by a feedback path - 4 transistors for storage - 2 transistors for access SRAM is fast and expensive -Used for Cache DRAM is cheaper and slower -Used for main memory

Memory Requirements An ideal computer memory would have -Zero access time -Infinite capacity -Zero cost -Infinite bandwidth (for multiple parallel access)

-Bigger implies slower -Higher cost

Memory addresses A memory address is a binary number. The number of bits needed to specify that number, determines the maximum size of the memory. Locations Each location can store several bits Nearly all computer manufactures have standardized on storing 8 bits per location. 8 bits is called a byte.

Representing Info with 1s and 0s A number gives the position of a character (symbol) in a standardized table of characters. American system for coded information interchange (ASCII) We only need 8-bits for this.

Words and Word Length In modern computers, bytes are generally grouped into 4-byte or 8-byte words and instructions manipulate an entire word as a single entity. The number of bits in a word is called the word length The word length reflects the structure and operation of a computer – Register sizes – Maximum data transfer between processor and memory in a singleoperation– Data bus size – Largest possible physical address size

Word alignment To simplify design and to speed-up execution, many architectures require words to be aligned in memory at addresses that are multiples of the word size. This is called aligning on the natural boundaries.

Error Checking Modern memory is reliable. Memory controllers check for errors only on system start-up. Some memory chips require greater reliability, they have built-in error checking and use parity checks to discover errors. E.g., nuclear power plant monitors.

Parity Checking Ram These chips have an extra bit for every 8 bits of data.When data is being written the chip adds up the total number of 1s in each byte. -If the total is odd, the parity bit is set to 1 -If the total is even, the parity bit is set to 0 Because it always results in an even number of 1s, it is known as an Even Parity Scheme.

Limitations of Parity Schemes It's possible to detect an error but it is not possible to identify the error, nor to correct it.

Mission-critical systems Mission-critical systems need a higher level of fault tolerance than parity checking can give. Error Correcting Codes (ECCs) These use multiple extra bits to identify multi-bit errors within a byte and can correct single bit errors.

Endianness refers to how the bytes of a word are stored in memory. Big Endian: The most significant byte is stored in the lowest address being used to hold the world; Byte 2 is stored in the next highest address.Little Endian: The most significant byte is stored at the highest address being used to hold the word, Byte 2 is stored in the next lowest address.

Locality of Reference The tendency for items close to each other being accessed multiple times over a short period of time.

Samphire

Samphire mov instructions

Assembler

Machine Code

Explanation

MOV

AL,15

D0 00 15

AL = 15

Copy 15 into AL

MOV

BL,[15]

D1 01 15

BL = [15]

Copy RAM[15] into BL

MOV

[15],CL

D2 15 02

[15] = CL

Copy CL into RAM[15]

MOV

DL,[AL]

D3 03 00

DL = [AL]

Copy RAM[AL] into DL

MOV

[CL],AL

D4 02 00

[CL] = AL

Copy AL into RAM[CL]

  • [ ] = memory first register always a destination You must write to a register before writing to memory.

Samphire Arithmetic and Logic Instructions

Assembler

Machine Code

ADD

AL,12

B0 00 12

AL = AL + 12

SUB

BL,15

B1 01 15

BL = BL - 15

MUL

CL,03

B2 02 03

CL = CL * 3

DIV

DL,02

B6 03 02

DL = DL / 2

AND

AL,10

BA 00 10

AL = AL AND 10

OR

CL,F0

BB 02 F0

CL = CL OR F0

XOR

AL,AA

BC 00 AA

AL = AL XOR AA

Samphire

Every hex digit connects to 4 bits. They are an example of Amdahl's law. (Make the common case fast)

Samphire Control: Flow Instructions SR - Status register

Conditional jump instructions include:– jz label ; jump to the label if the zero flag is set – jnz label ; jump to the label if the zero flag is not set– js label ; jump to the label if the sign flag is set – jns label ; jump to the label if the sign flag is not set – jo label ; jump to the label if the overflow flag is set – jno label ; jump to the label if the overflow flag is not set

Reading and writing from/to PORTS The IN instruction takes input from a specific port e.g., Port 00 (this port is linked to the keyboard in Samphire).

The Operating System Level

Operating System An OS adds a variety of new instructions and features on top of the ISA level. The operating system level is known as the OSM (operating system level) level.

The OSM-level instruction set is a complete set of instructions available to application programmers.

23/11/22 Virtual Memory

In the most general sense, an operating system's tasks fall into six categories:

  1. Processor management
  2. Memory management
  3. Device management
  4. Storage management
  5. Application interface
  6. User interface

Memory

Magnetic Disks Disk substrate coated with magnetizable material. Substrate used to be aluminum, now it is glass. Read and Write Writing A changing current produces a magnetic field in the head. Reading

Formatting the disk The process of low-level formatting establishes the sectors where a program is stored within the drive.