Programming I – CPU, Machine Cycle, Pipelining, RISC/CISC & Data Representation

Review of Previous Coverage

• The course has already introduced four fundamental pillars:
  • Computer (general concept & history)
  • Computer System (integration of hardware + software + users)
  • Computer Hardware (physical/electronic components)
  • Computer Software (intangible instructions that direct hardware)

Computer Software

• Two Grand Families
  • System Software – software that manages the computer itself.
  • Operating System (OS)
    • Controls the use of memory, processor, devices
    • Provides user-interface & file-management services
  • Utility Programs
    • Diagnose, maintain, optimise (e.g. disk defragmenter, antivirus)
  • Device Drivers
    • Tiny, dedicated programs that let OS communicate with peripherals (printer, scanner, keyboard…)
  • Firmware
    • Software permanently embedded in hardware (non-volatile)
    • BIOS/UEFI: first code executed at power-on, sets up the hardware & starts the OS
  • Programming-Language Translators
    • Assemblers, Compilers, Interpreters transform human-readable code → machine code
  • Application Software – programs that perform user tasks (personal, educational, business)

The System Unit

• System Unit (Chassis/Case) – metal or plastic enclosure that houses electronic components.
• Motherboard (System Board) – the primary flat circuit board containing:
  • CPU Socket & Mounting Points
  • Northbridge (high-speed, memory/graphics controller)
  • Southbridge (I/O controller)
  • Chipset (Bus Controller) – orchestrates data flow on system & expansion buses
  • Slots & Connectors
  • $ext{DRAM slots} \quad IDE\;Connectors \quad AGP/PCI/PCIe\;slots \quad 20\text{-pin ATX power}$
  • CMOS Battery – backs up BIOS settings
  • Rear I/O panel: PS/2, serial, parallel, USB, Ethernet, audio
• Chip
  • Piece of silicon/germanium etched with Integrated Circuits (ICs) (resistors, capacitors, transistors)
  • DIP (Dual-Inline Package) – through-hole mounting package for memory ICs
  • PGA (Pin-Grid Array) – package for many modern CPUs
• Heat Management
  • Heat Sink, Fan, Heat Pipes remove thermal energy from CPU & GPU

Memory Hierarchy & Types

• Volatile vs Non-Volatile
  • Volatile: loses data without power (RAM, Cache)
  • Non-Volatile: retains data (ROM families, Flash)
• Registers – inside CPU, fastest, word-sized
• Cache – small SRAM on/near CPU, multi-level (L1, L2, L3)
• Main Memory (RAM)
  • DRAM – inexpensive, needs refresh
  • SRAM – faster, no refresh, used for cache
  • MRAM – magnetic, non-volatile research memory
• Secondary ROM/Flash Variants
  • ROM / PROM / EPROM / EEPROM / Flash – differ in re-programmability
• Disk Cache – RAM that buffers disk reads/writes

Central Processing Unit (CPU)

• Definition: Highly complex IC that fetches, decodes & executes instructions.
• Core Internal Sections
  • Control Unit (CU) – coordinates all operations
  • Arithmetic-Logic Unit (ALU) – performs $+\ ,\ -\ ,\ \times\ ,\ \div$ and logical (AND, OR, NOT) & comparison operations
  • Registers
  • Specific-task (e.g.
    • Accumulator in ALU
    • Decoder control register)
  • General-purpose (data/addresses)
  • System Clock – quartz crystal generating regular ticks
  • $\text{Clock Speed}=\text{ticks per second (Hz)}$
  • Typical PC range $\approx 3\,\text{GHz}=3\times10^{9}\,\text{Hz}$
  • Alternative metrics: $\text{MIPS}$, $\text{MEGAFLOPS}$ (floating-point)
  • Cache (on-chip, multi-level)
  • Buses (control, address, data) – define bit-width & throughput
  • Co-processor(s) – specialised chips (e.g. GPU, FPU)

Machine Cycle (Fetch–Decode–Execute–Store)

• Four Basic Operations
  1. Fetch instruction/data from memory
  2. Decode into machine signals
  3. Execute via ALU/CU
  4. Store result back to memory (not to external storage!)
• Timing
  • I-Time: Fetch + Decode interval
  • E-Time: Execute + Store interval
• Worked Example (multiplying $100\times52$)
  • Step 1 (Fetch): CU fetches operands & op-code
  • Step 2 (Decode): CU interprets "multiply"
  • Step 3 (Execute): ALU computes $5200$
  • Step 4 (Store): result $5200$ written to RAM then displayed

Pipelining & Parallel Processing

• Parallel Processing
  • Multiple processors/co-processors run sub-programs simultaneously
  • Requires specially written software (e.g. weather modelling supercomputers)
• Instruction Pipelining
  • Processor divided into "stages" $S<em>1, S</em>2, \dots, S_m$
  • While stage $S<em>1$ fetches instruction $I</em>{n+1}$, stage $S<em>2$ decodes $I</em>n$, stage $S<em>m$ stores $I</em>{n-m+1}$ → throughput ↑
  • Reduces bus bottlenecks; central to RISC design
• Illustrative Diagram
  • $\text{Data In} \rightarrow R<em>1C</em>1 \rightarrow R<em>2C</em>2 \rightarrow \dots \rightarrow R<em>mC</em>m \rightarrow \text{Data Out}$

RISC vs. CISC Architectures

• CISC (Complex Instruction Set Computing)
  • Large, variable-length instruction set; many addressing modes
  • Emphasis on hardware capabilities (micro-programming)
  • Single instruction may perform complex task (e.g. string copy)
  • Pipeline implementation is harder
  • Example: x86 desktop/laptop CPUs
• RISC (Reduced Instruction Set Computing)
  • Small, fixed-length, simple instruction set
  • More registers, fewer addressing modes
  • Heavy reliance on compiler for instruction sequencing
  • Pipelining is easy & prominently used → high IPC (instructions per cycle)
  • Examples: ARM (smartphones/tablets), MIPS (embedded), PowerPC (historic Macs)
• Trade-off Summary
  • CISC: hardware complexity, potentially fewer instructions executed
  • RISC: simpler hardware, more instructions but higher pipeline throughput, less crash-prone for engineering/graphic tasks

Grid & Distributed Computing

• Grid Computing
  • Aggregates idle CPU cycles/storage across geographically dispersed nodes to form a “virtual supercomputer”
  • Crosses organisational/architectural boundaries → enormous collaborative power
  • Requires middleware to schedule & secure jobs
• Distributed Computing
  • Application components placed on different networked machines
  • Heterogeneous OS/hardware possible
  • Example: Word-processor where GUI editor (PC1) calls spell-checker (PC2) & thesaurus (PC3)
  • Needs standards (e.g. CORBA, REST, gRPC) for object communication

Data Representation

Analog vs Digital

• Analog: continuous waves (human voice, temperature)
• Digital: discrete $0/1$ states (Boolean logic) – easier noise immunity & storage

Basic Units

• Bit – smallest data unit (binary digit)
• Byte – $8$ bits (ASCII/EBCDIC); $16$ bits for some Unicode encodings
• Hierarchy of Byte Multiples (binary definitions)
  • $1\,\text{KB}=1024\,\text{bytes}$
  • $1\,\text{MB}=1024\,\text{KB}=1024^{2}\,\text{bytes}$
  • $1\,\text{GB}=1024^{3}\,\text{bytes}$
  • $1\,\text{TB}=1024^{4}\,\text{bytes}$
  • (continues → PB, EB, ZB, YB)

Coding Schemes

• ASCII – $7$-bit (plus parity) standard for characters (used in PCs)
• EBCDIC – $8$-bit IBM mainframe code
• Unicode – $16$/$32$-bit universal character set, reserving $6000$ codes private & $30000$ for future

Example (scancode → ASCII)

1. User presses Shift + D → keyboard emits scancode
2. Scancode sent to system unit
3. System translates → ASCII $01000100_2$ (decimal $68$, hex $44$) stored in RAM
4. When needed, binary is rendered as glyph ‘D’ on screen

Number Systems Conversion Table (excerpt)

• $0000<em>2 = 0</em>{10} = 0_{16}$
• $1010<em>2 = 10</em>{10} = A_{16}$
• $1111<em>2 = 15</em>{10} = F_{16}$
• $10000<em>2 = 16</em>{10} = 10_{16}$

Binary Circuit Mapping

• Electronic state ↔ Bit value
  • ON / Charged → $1$
  • OFF / Discharged → $0$

Ethical, Practical & Real-World Notes

• Efficient instruction design (RISC pipeline) reduces energy use – vital in mobile devices
• Grid computing supports global scientific research (e.g. climate modelling, CERN data analysis)
• Firmware security (UEFI) is critical: compromised firmware can bypass OS-level defences
• Data representation choices (Unicode) ensure inclusivity for non-Latin languages

Key Formulae & Numerical References

• $\text{MIPS}=\frac{\text{Million Instructions}}{\text{Second}}$ (performance metric)
• $1\,\text{Hz}=1\,\text{cycle per second}$ ; $1\,\text{GHz}=10^{9}\,\text{Hz}$
• Cache levels: L1 (≈64 KB), L2 (≈256 KB–8 MB), L3 (≈8–64 MB) depending on architecture

Connected Topics & Prior Principles

• Boolean algebra & logic gates underpin ALU operations
• Von Neumann architecture: single memory stores both instructions & data – source of the fetch/decode/execute loop.
• Moore’s Law historically governed chip density; pipelining/parallelism now compensate for clock-speed plateau (thermal limits)

Study Reminders

• Understand every step of the machine cycle; be able to draw pipeline timelines.
• Practise conversions among binary, decimal, hexadecimal.
• Compare RISC vs CISC not only by definitions but by practical examples (ARM smartphone vs x86 laptop).
• Sketch motherboard layout; label Northbridge, Southbridge, slots.
• Explain how grid computing differs from a simple LAN render-farm (cross-organisation resource pooling).