PDF Review

Week One:

Part 1: Verilog introduction (Slide 1-20)

Page 8:
Q: What is a reg? Makes a variable a register. Where it can hold a value across procedural assignments.
Q: Why? When using procedural blocks (pb) (“always, initial, task, and function”), you can use a ‘reg’ variable within them where you may assign it to a value. A ‘wire’ variable can only be assigned outside of a pb.

  1. Sequential Logic: When modeling sequential logic elements like flip-flops or latches, you'll use a reg because you'll be making assignments to it within an always block.

  2. Temporary Variables in Procedural Blocks: You might need intermediate variables in tasks, functions, or always blocks to hold temporary values. These variables should be of type reg.

  3. State Machines: When designing state machines, the current state is typically stored in a reg because it's assigned within an always block.

  4. Non-Continuous Assignments: In scenarios where you don't want an assignment to always be active (unlike with assign statements), you would use a reg and assign its value inside a procedural block.

    In summary, you would use reg whenever you need a variable that can be assigned values within procedural constructs in Verilog. In system verilog, would use logic (datatype) as reg.

Q: What is a wire? A component made.

Q: What are these datatypes’ sizes? Depends. I must define width definition. By default a 1-bit value variable if not stated. Max is 32 bits.

wire w; // 1-bit wire        wire [N-1:0] w; // N-bit wire
reg r;// 1-bit reg         reg [N-1:0] r; // N-bit reg
Ex: Y = 1’b1; // Means that 1-bit one value assigned

“Module describes a component. There is a relationship bet. I/O.”

Scope of module: Everything that is within that module.

  • In Verilog, each module has its own namespace, meaning the variables, nets, and other identifiers you declare inside one module won't be directly visible in another module.

  • Local variables in one module is visible to that module only.

  • Use of ports are done to access these local variables’ datas from different modules. Port Example below:

    module module1(output reg a); 
// ... some logic that assigns a value to 'a
endmodule
    module module2(input b);
// ... some logic that uses the value of 'b'
endmodule
    module top();
wire interconnect;
module1 m1(.a(interconnect)); // 'a' of module1 is connected to 'interconnect'
module2 m2(.b(interconnect)); // 'b' of module2 is also connected to 'interconnect'
endmodule

OR 

module top (input A, B);
module1 m1 (A, interconnect); // this is the m1 instance of module1. 
module2 m2 (B, interconnect); // ...
endmodule

    Explanation: In the example above, module1 outputs a value on ‘a', which is connected to the wire ‘interconnect'. module2 takes an input ‘b' which is also connected to the same interconnect. This is how data is shared between the modules.

    • Often doing this for simulation probing (test benches) than actual data sharing.

    Q: What if I want to share a variable but not let it be modified?

    • If you want to share a variable (signal) value with other modules without allowing those modules to modify it, declare the signal as an output in the source module and input in the destination modules.

  • The ‘always' block. A procedural block of code where it always run, describes a hardware behavior. Done in sequential block. Common examples: “…@(*),…@(posedge).

  • Use of conditional behavior to establish this continuancy for one variable that is dependent on a changing value variable.

  • True or false? Declare reg variable before an always block is good. (True).

    Clock Signal

    Level Sensitivity (X,Z) vs. Time Sensitivity(posedge, rst) on a pb.

    Blocking Assigns concept

    Q: When to use <= or = (Non-Blocking/blocking assigns)?

  • (“=”) The blocking assignment means the right-hand side is evaluated and the result is immediately assigned to the left-hand side. Subsequent statements have to wait until the current statement is executed.

    always @(posedge clk) begin
a = b;
c = a;
end

    Here, the value of c will be the current value of a (the value of b) from the same time step because both assignments happen effectively at the same time, at the end of the block.

  • (“<=”) Non-blocking assignments allow all the right-hand sides in the block to be evaluated first, and then the assignments to the left-hand sides occur concurrently (at the same time).

    This is useful for describing parallel hardware operations, like multiple flip-flops being updated on a clock edge.

    always @(posedge clk) begin
    a <= b;
    c <= a;
end

    In this case, the value of c will be the old value of a because the assignment c = a; does not wait for a = b; to complete.

    When to use which?

    Use Non-blocking (<=) for:

    • Sequential logic, such as flip-flops.

    • Whenever you have multiple assignments in an always block that are meant to happen at the same time, like on a clock edge.

    • Vital for verilog to be able to model memory.

    Use Blocking (=) for:

    • Combinational logic inside procedural blocks.

    • When the order of operations matters and one operation depends on the result of a previous one within the same time step.

RULES

  1. Within one module, a variable can be assigned in one procedural block ONLY. Ideally, a variable shouldn't be driven by multiple always blocks (or other procedural blocks). This could lead to multiple drivers for the same net in the synthesized design, which is generally not desired and might not be synthesizable, depending on the target technology.

  2. A continuous assignment can’t be done in a procedural block.

  3. Variables assigned a value in a continuous assign statement must be declared wire (Verilog) .

    1. Assigned in a always block must used reg(Verilog).

  4. In SV, logic datatype be used for either reg or wire. And you may use “assign” on variable outside of procedural and in Pb.

For synthesizable code, loops are often used for generating repetitive structures or performing operations across arrays/buses. In this context, there are stricter rules:

  1. Static Loop Bounds: The start and end values of the loop, as well as the increment, should be static (i.e., constants). This ensures that the synthesizer can unroll the loop and determine the amount of hardware resources required.

    
// Good for (i = 0; i < 8; i = i + 1) ... 
// Bad (assuming max_val is not a constant) 
for (i = 0; i < max_val; i = i + 1) ...

Part 2: FPGA (Slide 20→ 38)

Slide 20

  • The FPGA in the Max 10 DE-10 Lite is the black square in it.

  • The FPGA board has 50k programmable logic units. 3MBs embedded memory. 4 Phase Lock Loops (PLL)

  • Produces a 5V and 3.3V DC power.

GPIO - a digital interface where it shows how you may connect external systems to the board.

  • (Slide 26) Allows Arduino connection. 7 segment display.

  • (Slide 31) Platform Designer, use of this tool in Quartus. Where you can connect various inputs into a certain fashion for your custom system configuration.