Computer Organisation & Architecture – Module 1 Comprehensive Notes

Institution Vision & Mission

• RSET Vision

  • Evolve into a premier technological & research institution.

  • Mould eminent professionals with creative minds, innovative ideas & sound practical skill.

  • Shape a future where technology enriches mankind.

• RSET Mission

  • Impart state-of-the-art knowledge in technological disciplines.

  • Inculcate social consciousness & human values.

  • Enable graduates to face life’s challenges with courage & conviction.

• CSE Department Vision

  • Centre of Excellence in Computer Science & Engineering, catering to national & international research / professional needs.

• CSE Department Mission

  • Inspire & nurture students in up-to-date CS&E knowledge, ethics, team spirit, leadership, innovation & creativity to solve societal problems.

Course Outcomes (COs)

• CO1 Recognise relevance of basic components, I/O organisation, processing unit in a digital computer.

• CO2 Explain arithmetic circuits & basic processor-design components.

• CO3 Explain pipelining concepts, hazards & instruction pipelining principles.

• CO4 Demonstrate computer memory hierarchy & design cache memory.

• CO5 Summarise I/O subsystem, interrupts, USB devices, hard-disk working.

• CO6 Explain architecture, modes, instruction set & programming concepts of modern processors.

Syllabus Snapshot (6 Units)

• Unit I – Basic computer structure, memory, addressing, processing unit, single & multiple bus organisation.

• Unit II – Register-transfer logic, arithmetic/logic/shift µ-ops, multiplier & divider hardware, processor logic design.

• Unit III – Pipelining, 5-stage RISC, hazards, multi-stage, scheduling, speculative / out-of-order execution & ROBs.

• Unit IV – Memory hierarchy, SRAM/DRAM/Flash, caches (mapping, replacement, write strategies, optimisation).

• Unit V – I/O organisation, interrupts, DMA, USB, PCI, hard-disk & RAID, RISC-V intro.

• Unit VI – Case studies: x86, MASM, VEGA, ARM, GPU intro.

Module 1 Focus (slides covered)

• Basic structure of computers.

• Memory locations, addresses, endianess.

• Instruction & instruction sequencing, addressing modes.

• Processing unit & instruction cycle.

• Single-bus vs multi-bus organisation.

What Is a Computer?

• Sophisticated electronic calculating machine.

• Core functions:

  • Accept input.

  • Store instructions & data.

  • Process per stored instructions.

  • Output results.

Types of Computers

• Personal Computers (desktops).

• Notebooks / Laptops.

• Tablets / Smartphones.

• Workstations (engineering, graphics, scientific).

• Embedded computers (cars, appliances, industry).

• Servers (multi-user, web, DB, network).

• Enterprise systems / Mainframes (high reliability, scalability).

• Supercomputers (large-scale numerical calc: weather, CFD, etc.).

Computer Organisation vs Architecture

• Organisation = how hardware components operate & interconnect (functional implementation).

• Architecture = structure & behaviour as seen by a programmer (instruction set, formats, addressing).

• Architecture specifies functional modules; organisation realises them.

Information Inside a Computer

• Instructions tell the machine to transfer data or perform ALU ops. Stored sequentially as a program in memory.

• Data (operands) = numbers, encoded characters, any digital info represented as bits.

Functional Units

• Five independent components:

  • Input Unit

  • Output Unit

  • Memory Unit

  • Arithmetic & Logic Unit (ALU)

  • Control Unit (CU)

Input Unit

• Interfaces e.g. keyboard, mouse, touch, 8255 PPI.

• Accepts external binary data → presents to processor/memory.

Memory Unit

• Stores program code, data, results.

• Primary (main) memory – fast semiconductor (RAM, ROM).

  • RAM – volatile, holds run-time code/data.

  • ROM – non-volatile, holds firmware (BIOS, POST, drivers).

• Secondary memory – non-volatile, larger & cheaper (HDD, SSD, DVD, Flash).

• Memory hierarchy trade-off: capacity ↑ ⇒ speed ↓ ⇒ cost/bit ↓.

  • Registers → Cache → Main RAM → Secondary storage.

• Word length = # bits transferred per access (8, 16, 32, 64, 128 bits).

• Units

  • $1\,\text{Byte}=8\,\text{bits}$

  • $1\,\text{KB}=2^{10}\,\text{B}=1024\,\text{B}$

  • $1\,\text{MB}=2^{20}\,\text{B}$, $1\,\text{GB}=2^{30}\,\text{B}$, $1\,\text{TB}=2^{40}\,\text{B}$.

ALU

• Executes arithmetic (+,−,×,÷) & logic (AND, OR, NOT, compare) ops.

• Operands loaded from registers; result back to registers or memory.

• Receives operands, opcode & outputs result + status flags (Zero, Carry, etc.).

Control Unit

• Decodes machine instructions, generates timing & control signals.

• Synchronises all unit activities (often via system clock).

• Implements Fetch–Decode–Execute cycle.

Registers (CPU Internal Storage)

• Fastest storage; all data must be in a register before ALU use.

• Key special-purpose registers:

  • Program Counter (PC) – address of next instruction.

  • Instruction Register (IR) – holds current instruction.

  • Memory Address Register (MAR) – address for memory access.

  • Memory Data Register (MDR) – data being read/written.

• General-purpose registers (scratchpad) for data & intermediate results.

• “More & bigger registers ⇒ faster/stronger CPU”.

Fetch–Execute Cycle (single instruction)

1. Fetch – PC → MAR; memory read; fetched word → MDR → IR; PC += word-size (e.g., $+4$ in 32-bit byte-addressable).

2. Decode – CU interprets opcode & addressing mode.

3. Execute – ALU / memory / I/O operations per instruction.

4. Write-back results; update PC or branch.

5. Handle interrupts (device raises signal; processor executes interrupt-service routine).

Computer Buses

• System Bus = shared communication pathway connecting CPU, memory, I/O.

• Composed of:

  • Data Bus (bi-directional) width ⇒ throughput.

  • Address Bus (uni-directional CPU→devices) selects source/destination.

  • Control Bus (read/write, interrupt, clock, bus-request, etc.).

Bus Structures

• Single-Bus – all units share one bus → simple, low cost, but one transfer at a time (bottleneck).

• Two-Bus – separate Memory & I/O buses; better concurrency & speed, higher cost; CPU mediates I/O transfers.

Memory Addressing Concepts

• Memory has $2^{k}$ addressable locations when address bus = $k$ bits.

  • Example: $k=32$ byte-addressable ⇒ $2^{32}=4\,\text{GB}$ capacity.

• Byte addressability – every byte has unique address; words may span multiple addresses.

• Word alignment – efficiency when word starts at address multiple of word size.

Endianess

• Big-Endian – most-significant byte (MSB) stored at lowest address. Example: Motorola 68K, SPARC.

• Little-Endian – least-significant byte (LSB) at lowest address. Example: Intel x86, ARM.

• 32-bit pattern $0x12345678$ @ address $0x00400000$ stored:

  • Big-Endian → $12\,34\,56\,78$

  • Little-Endian → $78\,56\,34\,12$.

Basic Memory Operations

• Fetch / Read / Load – transfer data from memory → CPU (memory unchanged).

• Store / Write – transfer CPU word → memory (overwrites old data).

Sample Numerical Problems

1. 32-bit address, byte-addressable ⇒ $2^{32}=4\,096\,\text{MB}=4\,\text{GB}$.

2. 24-bit address, word-addressable, word = 4 B ⇒ $2^{24}\text{ words}=16\,\text{MB}\times4=64\,\text{MB}$.

3. 16-bit address, byte-addressable, word = 4 B ⇒ bytes = $2^{16}=65\,536$, words = $65\,536/4=16\,384=16\,\text{K}$.

Instruction Formats

• Three-Address ADD R1,R2,R3 (R3←R1+R2).

• Two-Address ADD R1,R2 (R1←R1+R2).

• One-Address (Accumulator) ADD B (AC←AC+B).

• Zero-Address (Stack) operands implicit on stack top (PUSH A, PUSH B, ADD).

Worked Example – Compute $y=x^{2}+2x+3$

• Three-address sequence (R-style shown in slides).

• Two-address & one-address variants also provided (see slides for detailed steps).

Addressing Modes

• Effective Address (EA) = final memory address CPU uses.

• Table of modes (generic):

  • Immediate #K operand = constant $K$ (no memory reference).

  • Register Direct Ri (EA = Ri).

  • Direct / Absolute LOC (EA = LOC).

  • Register Indirect (Ri) (EA = [Ri]).

  • Memory Indirect (LOC) (two-level).

  • Indexed / Displacement X(Ri) (EA=[Ri]+X).

  • Base + Index (Ri,Rj) (EA=[Ri]+[Rj]).

  • Base + Index + Offset X(Ri,Rj) (EA=[Ri]+[Rj]+X).

  • Relative X(PC) (EA=[PC]+X) – used for branches.

  • Auto-Increment (Ri)+ (EA=[Ri]; Ri←Ri+δ).

  • Auto-Decrement -(Ri) (Ri←Ri-δ; EA=[Ri]).

• δ = 1 for byte, 2 for 16-bit, 4 for 32-bit operands.

Example Trace of Mixed Modes (slide list 1-12)

• Students asked to identify modes for instructions like Move #500,R0 (Immediate) , Add 4(R0),R1 (Index), Add [R2],[R0] (Memory Indirect), etc.

Internal CPU Organisation (Single-Bus)

• Registers, ALU, multiplexers, MAR/MDR connected by common internal bus.

• Control signals:

  • Rin, Rout gate registers to/from bus.

  • ALU function select (Add, Sub, XOR, etc.).

  • MUX select (Y vs constant 4).

• Register Transfer Example Move R1,R4 → R1out, R4in.

• ALU Example Add R1,R2,R3 → 3 micro-steps (move R1→Y, add R2, store Z→R3).

Memory Interface Signals

• Read, Write, MDRinE, MDRoutE, WMFC (Wait for Memory-Function-Completed).

• Example micro-sequence for Move (R1),R2 (read from memory address in R1 then load R2).

Instruction Execution Sequencing Examples

• Detailed micro-operations for Add (R3), R1 (fetch op, read operand, execute, write-back).

• Unconditional & conditional branch: PC update by offset X (signed). Example offset $+16$ when jumping from $2004\to2020$.

Multi-Bus (Three-Port Register File) Organisation

• Register file with two read ports (A,B) & one write port (C) allows parallel operand fetch & result write in one clock.

• Buses A & B feed ALU; result on C.

• Incrementer unit adds $+4$ to PC concurrently.

• Reduces micro-steps (e.g., Add R4,R5,R6 completes in 4 control steps vs 7+ on single bus).

Tutorials (Sample Control Sequences)

• Provided sequences for single-bus CU to execute:

  • Add #NUM,R1 (immediate).

  • Add NUM,R1 (direct).

  • Add [NUM],R1 (memory indirect).

  • Add R1,NUM & store result back to NUM.

Real-World Example – ATM Withdrawal Flow

• Input: user inserts card & PIN.

• CU verifies; ALU checks if balance ≥ request & subtracts.

• CU commands I/O to display confirmation, dispense cash, print receipt.

Key Takeaways & Exam Pointers

• Memorise functional units, buses & register roles.

• Practice endian conversion & word-alignment implications.

• Be fluent in calculating memory size: \text{bytes}=2^{\text{address_bits}} (byte-addressable) or $\times\text{word-size}$.

• Understand every addressing mode & identify from assembly syntax.

• Rehearse micro-operation sequences for instruction execution (fetch, decode, execute).

• Compare single-bus vs multi-bus design trade-offs (cost vs performance).

• Relate concepts to real systems: x86, ARM, RISC-V, GPU (Unit VI follow-up).

References (for deeper study)

• M. Morris Mano – Digital Logic & Computer Design (2017).

• Patterson & Hennessy – Computer Organisation & Design, 6/e (2021).

• Kai Hwang – Computer Architecture & Parallel Processing.

• Steve Heath – Microprocessor Architectures (Elsevier).

• Supplementary: Mano – Computer System Architecture; Stallings; Chaudhuri; Rajaraman & Radhakrishnan; Messmer.