Unit I – Lecture 5: Standard-Cell Based VLSI Design

Session Objectives

Discuss and understand the Standard-Cell Based Design (SCBD) methodology.
Recognise its place within the broader spectrum of VLSI implementation methodologies.

Standard-Cell Based Design – Fundamentals

SCBD is a popular full-custom mask approach but uses pre-designed, re-usable logic cells (aka polycells).
All commonly used logic functions are provided in a Standard Cell Library (SCL).
- Library size: typically a few hundred cells (inverters, NAND, NOR, AOI/OAI, D-latch, flip-flop, etc.).
- Multiple drive-strength versions exist (e.g. inverter in standard, $2 imes$ , $4 imes$ sizes) to meet fan-out & speed needs.
Cells are laid out with fixed height, variable width → enables row‐based abutment.
Power (VDD) and ground (VSS) rails run horizontally along the top and bottom edges; neighbouring cells share common rails.
I/O pins placed on top/bottom edges for easy access by routing channels.

Standard Cell Library Composition & Characterisation

Each cell is fully pre-characterised for:
- Delay vs load capacitance curves.
- Circuit simulation (SPICE) models.
- Static-timing models.
- Fault models for test generation.
- Place-and-route abstract view (cell geometry, pin locations).
- Mask data / GDS-II.
Library must provide for multiple fan-in / fan-out options and different capacitive load ranges (e.g. $0.18\,\text{pF} \rightarrow 0.72\,\text{pF}$ for a $3$ -input NAND example).
Mandatory views per ASIC vendor:
- Physical layout, behavioural HDL model, detailed timing, wire-load, routing model, test strategy, schematic, icon symbol.

Cell Geometry, Layout & Placement Rules

Fixed cell height aligns diffusion regions, wells and routing tracks → seamless abutment.
pMOS devices placed near VDD, nMOS near VSS (mirrors conventional full-custom style).
Rows of cells separated by dedicated routing channels; advanced processes may use over-the-cell routing to shrink/erase channels.
Feed-through cell: a special empty/transparent cell that permits signals to pass through a row without logic computation, reducing wiring congestion.
Typical process example: $0.18\,\mu\text{m}$ CMOS, $7$ metal layers → cell diffusion completely hidden under upper-metal global routing.

Floor-Planning & Routing Strategies

Chip area inside the I/O frame filled with rows or columns of standard cells.
Multiple macro-blocks (clock gen, ALU, control) can be placed; power/ground delivered from both sides when blocks split.
Routing hierarchy:
1. Local intra-row wiring (short segments, lower metals).
2. Channel / over-cell inter-row wiring (mid metals).
3. Global buses & clock meshes (upper metals).
Optional signal bus insertion between rows for shared inputs/outputs.

Performance Optimisation & CAD Tool Support

Automated Place-&-Route (P&R) tools attempt to minimise:
- Wire-length (hence delay & area)
- Routing congestion
- Power dissipation
Parasitic extraction (R, C) → timing analysis → identification of critical paths.
Gate sizing / cell swapping on critical paths to satisfy timing.
Widely used for control logic of microprocessors & DSPs; entire full-custom chips can also be built exclusively from SC.

Standard Cell vs Other Design Styles

Sea-of-Gates / Gate-Array: pre-diffused transistors, only metal programmed; faster prototyping but lower density.
Full-Custom: transistor-level optimisation; highest density/performance, longest design time.
Programmable Logic (SPLD/CPLD/FPGA): maskless, field-programmable; fastest TTM, lowest density & speed.
Semicustom (SCBD) offers a middle-ground: automation with moderate performance-density trade-off.

ASIC Cell Library Requirements

To minimise interconnect overhead:
- Provide feed-through cells.
- Offer multiple metal layers (e.g. $7$ ) to route over cells.
Each library cell must include the comprehensive set of views/models listed above to enable reliable synthesis, simulation, test and routing.

Compiled Cells & Automated Generation

Problem: libraries need re-layout & re-characterisation for every process node.
Compiled-cell flow:
1. HDL/Spice schematic generation.
2. Transistor geometry derived (W/L sizing).
3. Devices placed into pre-defined architecture (fixed height, power rails, pins).
4. Symbolic routing, compaction, DRC fix.
Supports parameterised drivers & sizes for performance/power trade-off.

Macro-, Mega-cells & Intellectual Property (IP)

Standard cells inefficient for large regular blocks (multipliers, memories).
Macrocell / Megacell = higher-level reusable block.
- Hard macro: Function + fixed physical layout (e.g. $256\times32$ SRAM, $32\times16$ multiplier). Pros: density, predictability. Cons: hard to port.
- Soft macro: Function + netlist, no fixed layout; physical sizing decided later. Easier portability; aspect ratio flexibility.
  • Generator inputs: parameters, constraints → outputs: standard-cell netlist + timing constraints.
Intellectual Property (IP): 3rd-party reusable blocks of increasing complexity (embedded CPUs, DSPs, PCI cores, FFTs, MPEG codecs). Analogy to software libraries.
- IP ecosystem mirrors large-scale SW projects; often sold/licensed with accompanying toolchains (compilers, test-benches).

Semi-Custom Design Flow

Design Capture: schematic/HDL/SystemC, behavioural descriptions, IP import.
Logic Synthesis: HDL → standard-cell netlist; macro insertion.
Pre-layout Simulation: verify function & estimated timing using wireload/parasitics.
Floorplanning: coarse placement of blocks; global power/clock planning.
Placement: precise cell co-ordinates.
Routing: detailed wire paths.
Extraction: create post-layout netlist with exact device sizes & parasitics.
Post-layout Simulation: final functional & timing verification.
Design Iteration: loop back if violations.
Tape-out: generate mask data file (GDS-II) → foundry.

Timing Closure & Physical Synthesis

Deep-sub-micron → interconnect dominates delay; predicting parasitics pre-layout is hard.
Timing Closure: iterative removal of timing violations – can take weeks per iteration.
Integrated Physical Synthesis: merges RTL synthesis with early P&R to reduce iterations.
- RTL + constraints → first-order placement → optimisation → detailed P&R.
- Cuts timing closure loops but demands sophisticated EDA tooling.
- Alternative: adopt regular, predictable structures in logic & layout.

Exceptions & Limitations of Standard Cell Approach

Not ideal when:
- Extreme performance required.
- Ultra-low power mandatory.
- Function is highly regular (e.g. large memories, multipliers) → prefer full-custom or hard macros.
Performance/density penalty grows with library abstraction and automation.

Review Points & Key Definitions

Standard-Cell Based IC Design: methodology using a pre-characterised cell library to automate majority of layout tasks while still requiring custom masks.
Feed-through Cell: empty/transparent cell enabling signals to traverse a row without logic, alleviating routing congestion.
Cell Library Features: multiple views (layout, HDL, timing, test, icon, schematic, routing, wire-load), fixed height, variable width, multiple drive strengths, characterised delay models.

Connections, Implications & Real-World Relevance

SCBD underpins most modern ASICs (smartphones, GPUs, FPGAs’ hard blocks), balancing TTM and performance.
IP reuse parallels software engineering – accelerates SoC design but raises licensing & trust issues.
Timing closure remains a key challenge; drives innovations in physical-aware synthesis and machine-learning-assisted P&R.
Ethical/practical angle: IP protection, vendor lock-in, and ensuring trustworthy 3rd-party blocks (security).

References

Sung-Mo Kang et al., “CMOS Digital Integrated Circuits”, 4th Ed.
Jan Rabaey et al., “Digital Integrated Circuits”, 2nd Ed.
D. M. Harris & N. Weste, “CMOS VLSI Design”, 4th Ed.
Jacob Baker, “CMOS Circuit Design, Layout and Simulation”, 2018.
J. P. Uyemura, “Introduction to VLSI Circuits and Systems”, 2015.
Douglas Pucknell & K. Eshraghian, “Basic VLSI Design”, 3rd Ed.