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Important Questions – 8086 Microprocessor

Memory Addressing and Capacity

Q1: The maximum memory that 8086 can address is D) 1 MB.

Internal Architecture

Q2: The internal architecture of 8086 is divided into D) BIU and EU.

Flag Register

Q3: The Flag Register in the 8086 is a B) 16-bit register with flags. This register contains flags that represent the state of the processor.

Bus Interface Unit (BIU)

Q4: The Bus Interface Unit (BIU) is responsible for A) Fetching instructions from memory.

Execution Unit (EU)

Q5: The Execution Unit (EU) contains B) ALU (Arithmetic Logic Unit).

Functions of a Microprocessor

Q6: The main function of a microprocessor is D) Processing.

Historical Context of Microprocessors

Q7: The processor that was first commercially available is C) 4004.
Q8: The first microprocessor was developed by B) Intel.

Address and Data Bus Characteristics

Q9: The 8086 address bus width is C) 20-bit.
Q10: The 8086 data bus is B) 16-bit.

Instruction Cycle

Q11: The basic instruction cycle is A) Fetch - Decode - Execute.
Q12: The Instruction Pointer (IP) is used to B) Point to the next instruction.

Memory Support and Architecture

Q13: The 8086 supports D) 1 MB of memory.
Q14: The BIU and EU work C) Simultaneously.
Q15: The instruction queue size in 8086 is C) 6 bytes.

Physical Address Calculation

Q16: The physical address is formed by B) Segment × 16 + Offset.

Processor Types

Q17: The 8086 is a B) 16-bit processor.

Chiplet Technology and Multi-core Processors

Q18: Chiplet technology means B) Multiple small chips.
Q19: Multi-core processors were developed due to C) Speed limitation.

Definition of Microprocessor

Q20: A microprocessor is B) CPU on a chip.

Flag Register Functions

Q21: The Flag register contains B) Status and control flags.
Q22: The 8086 belongs to B) Third generation of microprocessors.

Execution Unit Components

Q23: The Execution Unit contains B) ALU.
Q24: The BIU contains B) Instruction queue.

Types of Flags

Q25: Zero Flag indicates B) Zero result.
Q26: Carry Flag indicates B) Carry out.
Q27: Parity Flag checks B) Even/odd bits.
Q28: Overflow Flag indicates B) Arithmetic overflow.

Stack Management

Q29: Stack Pointer points to B) Stack top.
Q30: Base Pointer is used for B) Stack frame.

Register Functions

Q31: SI register is used for A) Source index.
Q32: DI register is used for A) Destination index.

Addressing Features

Q33: 8086 address lines are C) 20.
Q34: Maximum I/O ports in 8086 are C) 65536.

Input/Output Techniques

Q35: Isolated I/O uses B) Separate I/O space.
Q36: Memory-mapped I/O uses B) Memory space.

IN and OUT Instructions

Q37: IN instruction is used for B) Input.
Q38: OUT instruction is used for B) Output.

Control Signals

Q39: DT/R controls B) Data direction.
Q40: DEN signal enables B) Data bus.

Additional Signals

Q41: ALE is used for A) Address latch.
Q42: Minimum mode selected when MN/MX is A) 0.
Q43: Maximum mode is used in B) Multiprocessor environments.

Address Lines and Bytes

Q44: AD0–AD15 are C) Multiplexed.
Q45: BHE is used for B) High byte.

Signal Usage

Q46: READY signal is used for B) Wait states.
Q47: RESET must be high for C) 4 clocks.

Final Memory Support

Q48: 8086 can address C) 1 MB of memory.

Historical Generations

Q49: First generation used A) Vacuum tubes.
Q50: Second generation used B) NMOS.

Microprocessor Characteristics

Q51: Intel 4004 is C) 4-bit.
Q52: 8086 was developed by B) Intel.

Development Milestones

Q53: Protected mode introduced by B) 80286.
Q54: Cache first introduced in D) 4th generation.

Modern Processor Types

Q55: Pentium II is C) 32-bit.

Queue Types

Q56: Queue type in 8086 is B) FIFO.

DMA and Multiplexing

Q57: DMA uses A) HOLD/HLDA.
Q58: Multiplexed lines are A) AD0–AD15.

Segment Registers

Q59: Segment registers count is C) 4.
Q60: Code segment register is A) CS.
Q61: Data Segment register is B) DS.
Q62: Stack Segment register is C) SS.
Q63: Extra Segment register is D) ES.

Instruction Pointer Role

Q64: Instruction Pointer points to B) Next instruction.

Address Latch and Signals

Q65: ALE signal is used to B) Latch address.
Q66: HOLD signal is used for B) DMA request.
Q67: HLDA signal indicates B) Hold acknowledge.

Read and Write Signals

Q68: RD signal means A) Read.
Q69: WR signal means B) Write.

Memory and I/O Selection

Q70: M/IO signal selects A) Memory or I/O.

Count of Segment Registers

Q71: 8086 has C) 4 segment registers.

Memory Segmentation

Q72: Maximum memory segmentation size is B) 64 KB.
Q73: Each segment in 8086 is C) 64 KB.

Arithmetic Logical Unit

Q74: The ALU performs B) Arithmetic operations.

Control Signaling and Timing

Q75: Clock signal controls B) Timing.
Q76: Instruction queue improves A) Speed.

Pin Count of 8086

Q77: 8086 uses B) 40 pins.

Microprocessor Architecture

Q78: 8086 is classified as B) CISC (Complex Instruction Set Computing).
Q79: Interrupt flag controls B) Interrupts.

Debugging and Status Flags

Q80: Trap flag is used for A) Debugging.
Q81: Sign flag indicates B) Negative result.
Q82: Auxiliary carry is used in A) BCD operations.

Operational Modes

Q83: 8086 supports B) 2 modes (Minimum and Maximum).
Q84: Minimum mode is for A) Single processor.
Q85: Maximum mode is for B) Multiprocessor.

Decoder and Latch Usage

Q86: Decoder is used for B) Selecting memory.
Q87: Latch is used to A) Store address temporarily.

Component Types

Q88: 74F245 is a B) Transceiver.
Q89: 74F138 is a A) Decoder.
Q90: 74F374 is a A) Latch.

Addressing Techniques

Q91: Memory-mapped I/O uses B) Same memory space.
Q92: Isolated I/O uses B) Separate I/O space.

Data Transfer Instructions

Q93: IN instruction transfers data B) From port.
Q94: OUT instruction transfers data B) To port.

Register Details

Q95: DX register is used for B) I/O port address.
Q96: AX register is a B) 16-bit accumulator.
Q97: BX register is used as A) Base register.
Q98: CX register is used for A) Counting.

Pipeline Effectiveness

Q99: 8086 pipeline improves A) Speed.

BIU and EU Terminology

Q100: BIU stands for B) Bus Interface Unit.
Q101: EU stands for A) Execution Unit.

Pipelining Mechanism

Q102: 8086 uses pipelining by B) BIU and EU parallel.

Address Forms

Q103: Segment:Offset forms A) Physical address.

Introduction Year

Q104: 8086 was introduced in the year B) 1978.
Q105: 8086 was manufactured by A) Intel.

Bus Functionality

Q106: Address bus is used for B) Address.
Q107: Data bus is used for B) Data transfer.

Control Bus Usage

Q108: Control bus is used for B) Control signals.

CPU Interaction

Q109: READY signal is used to B) Insert wait states.

Interrupt Types

Q110: Interrupts are B) Signals.
Q111: 8086 supports D) 256 interrupt types.

Stack Growth

Q112: Stack grows in direction B) Down.

Stack Instructions

Q113: PUSH instruction B) Adds data to stack.
Q114: POP instruction B) Removes data from stack.

Data Transfer Instructions Overview

Q115: MOV instruction is used for B) Data transfer.
Q116: JMP instruction is B) Control transfer.
Q117: CALL instruction is used for B) Procedure call.
Q118: RET instruction means A) Return.

Instruction Queue Description

Q119: 8086 has an instruction queue of C) 6 bytes.
Q120: Main advantage of 8086 is B) BIU and EU parallel operation.

Conclusion

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مقدم من حيدر محمد غازي - جامعة دجلة.