Study Notes for Microprogrammed Control Unit

A control unit that generates control signals using conventional logic design techniques.

A more advanced technique that allows a microprogram to be initially loaded from an auxiliary memory (e.g., magnetic disk).
Employs writable control memory, which can be modified.

A type of control memory whose contents can be modified, allowing for changes in microprograms and instruction sets.

Represents control variables at any given time as a string of 1's and 0's, referred to as a control word.

Detailed low-level instructions used in CPUs to implement complex machine instructions.
Also known as micro-ops or μops.

Can be translated from a symbolic microprogram to its binary equivalent using an assembler.
Each line in the assembly language defines a symbolic microinstruction, divided into five fields:
- Label: Designates the microinstruction’s identity.
- Microoperations (µops): Specifies operations to be carried out.
- CD (Condition): Specifies conditions of status bits.
- BR (Branch): Specifies the branching type.
- AD (Address): Contains address value for next microinstruction.

A sequence of microinstructions representing a specific control routine.
Can use read-only memory (ROM) for control memory as microprograms typically don't require changes once the control unit is in operation.

Microinstructions can be encapsulated using subroutines to avoid redundancy.
Example: The sequence to compute the effective address of an operand can be reused across multiple routines.

Configuration typically involves control memory assumed to be ROM where all control information is permanently stored.
The Control Memory Address Register (CMAR) specifies the microinstruction address.
The Control Data Register (CDR) holds the microinstruction read from memory.
Microinstructions contain bits for initiating microoperations and addressing sequences.
Next Address Generator: Computes the address of the next microinstruction, which may be next in sequence or a different memory location.
The organization requires a two-phase clock for simultaneous microoperation execution and microinstruction generation.
This setup allows easy modification of control sequences by simply altering microinstructions.

Microinstructions stored in control memory are grouped, with each group specifying a routine.
Steps for executing a CPU instruction are detailed as follows:
- Step 1: Load the initial address into the Control Address Register (CAR).
- This address usually activates the instruction fetch routine.
- The instruction is fetched into the instruction register after this step.
- Step 2: Load the effective address of the operand from the instruction bits via a routine in control memory.
- May utilize various addressing modes specified in the instruction.
- Step 3: Generate microoperations that execute the instruction fetched from memory, corresponding to the opcode.
- Step 4: Increment the CAR to sequence through microinstructions required for instruction execution.
- Subroutine calls require an external register for return addresses.
- An unconditional branch microinstruction is executed to return to the fetch routine after the instruction is executed.

Control Memory's sequencer selects the next microinstruction's address based on:
- Increment: The incrementor selects the next microinstruction sequentially.
- Branching: Conditional and unconditional branching as specified in microinstructions.
- External Address Inputs: Mapped via logic circuits for advanced addressing.

Status bits provide parameter information needed for decision-making in the control unit (e.g., carry-out, sign bit).

Involves a special type of branch that specifies a branch to the first word in control memory that holds a microprogram routine.
A mapping process indicates how bits of instruction codes are transformed to addresses in control memory (e.g., leading zeros for important bits, clearing least significant bits).
Capacity of microprogram routines can be designed by addressing strategies that allocate memory efficiently.

Central to microprogrammed control understanding is the block diagram showing the organization of memory, the registers involved, and their interactions.
Memory Units:
- Main memory: Storage for instructions and data.
- Control memory: Storage for microprogram.
Registers: AC (Accumulator), PC (Program Counter), AR (Address Register), DR (Data Register), CAR (Control Address Register), and SBR (Subroutine Register).
Multiplexers: Facilitate information transfer among registers.
ALU (Arithmetic Logic Unit): Executes microoperations using data from AC and DR, storing results back into AC.

Microinstructions typically consist of 20 bits divided into four functional parts:
1. Fields F1, F2, and F3 outline microoperations split into three 3-bit segments capable of defining 21 unique operations.
2. CD Field: Selects status bit conditions.
3. BR Field: Specifies branch type (conditional/unconditional).
4. AD Field: Contains the address value, usually 7 bits wide, to specify addresses from control memory.

Components include control memory and the address selection circuits called a microprogram sequencer which presents addresses to control memory for execution.
The sequencer can be adaptable, utilizing registers for temporary address storage during looping and subroutine calling.
Comprises multiplexers to select input sources and logic circuits for output management.
Typical operations include incrementing addresses, branching, calling or returning from subroutines, all supported by internal structure dedicated to flexibility and modular capability.

The microprogrammed control unit utilizes a sophisticated address sequencing method to execute machine instructions efficiently, reducing hardware dependence and allowing for software-level control of the instruction flow.
Address selection based on conditions, program states, and external instructions creates a versatile architecture for dynamic instruction handling.
The architecture supports extensions and modifications through software changes rather than requiring extensive hardware rewiring, making it economically feasible for developers.