EEE378-Logic Simplification-Part1
Page 1: Course Overview
Course Title: EEE378: Digital Electronic II Logic Simplification
Semester: 1 2024/2025
Page 2: Disclaimer
Notes are strictly for USM lecture purposes only.
Prohibition on distribution or public sharing of materials.
Photos taken during lectures are for the instructor's teaching profile only.
Page 3: Course Objectives
Introduce basic concepts of combinational circuits.
Introduce entered-variable Karnaugh map (K-map).
Page 4: Limitation of Boolean Algebra
No guaranteed algorithm for finding the simplest form of expressions.
Intermediate results may not be in the simplest form.
Page 5: Implicant, Prime Implicant, and Essential Implicant
Implicant: A single minterm or grouped minterms on the K-map.
Examples: A'B'C', A'BC', A'BC, ABC, A'C', A'B, BC.
Prime Implicant (PI): A group of adjacent minterms.
Must cover all possible groups on K-map as permissible under its definition.
Contains larger groups; e.g., F(A,B,C) = Em(0,2,3,7).
Essential Implicant: A prime implicant that covers a minterm that no other prime implicant covers.
Examples: A'C' and BC are essential implicants, covering unique minterms.
Page 6: Finding Minimum Expression Using K-map
Draw K-map and place 1's in squares for corresponding minterms.
Identify prime implicants; groups must be in powers of 2.
List the minimized expression from essential prime implicants.
Ensure every remaining 1 is covered by selected implicants.
Page 7: Example of K-map Simplification
Boolean function: F(A,B,C,D) = IM(0,1,2,4,9,11,15)
Resulting minimized expression: F(A,B,C,D) = BC'D + AD' + A'CD + BCD'.
Page 8: Entered Variable K-map (EVM)
EVM is a variable-extended K-map for functions exceeding 4 variables.
Allows organization of m-bits into n-bits in K-map.
Example discussed involves using m=1.
Page 9: EVM Example
Given F = A'BCD + A'B'CDE + ABC'D'E' + A'BC'DE'.
Placement on K-map illustrated with variable E.
Each part of the expression loaded into specific cells.
Page 10: Reducing Size of K-map
Discusses reorganizing 4-variable functions into 3-variable K-map.
Comparison of outputs against the variable D.
Method involves complementing D where necessary within cells.
Page 11: Function Representation
Example expression representation involving combinations:
f(A,B,C) = f0.A'B'C' + f1.A'B'C + f2.A'BC' + f3.A'BC +...
Page 12: Constructing EVM Steps
Systematic method for entering variables into K-map.
Detailed representation and conditions for filled cells.
Page 13: Constructing EVM (Continued)
Numeric representations for entries and conditions to determine filled states.
Page 14: EVM Expression Construction
Principles for mapping variable entries and establishing values using simple logic principles.
Page 15: Size Reduction for K-map
Process involves preparing for K-map using entered variables, deriving outputs collaboratively through minterms.
Page 16: Logic Expressions Overview
Additional insights into expressions via min-terms and max-terms demonstration.
Page 17: Inspirational Quote
"If you can't fly, then RUN. If you can't run, then WALK. If you can't walk, then CRAWL. But whatever you do, YOU HAVE TO KEEP MOVING" – Martin Luther King, Jr.
Page 18: Acknowledgment
Thanks for attention to the lecture material.
Page 19: Course Continuation
Continued focus on Logic Simplification in Digital Electronics.
Page 20: Exercise Introduction
Given Boolean function description for simplification.
Mention of notation: M – maxterm, m – minterm, Monos – multiples of sums.
Page 21: Exercise Solution Overview
Direction to achieve simplified expression of the previously stated function via K-map.
Page 22: Truth Table Development
Steps to construct a truth table that correlates to the EVM process.
Page 23: K-map Derivation Steps
Instructions to redraw and derive minimal function from three-bit K-map.
Page 24: Reconfirmation of Simplified Function
Conclusions drawn leading to equivalent expressions from K-maps.
Page 25: Function Analysis with 4-bit K-map
Analyzing results utilizing both 3-bit and 4-bit maps for optimal outcomes.
Page 26: Exploring Variable Options
Consideration of switching the entered-variable from D to C.
Page 27: More Exercises
Additional problems given for EVM application and practice.
Function transformations stated for practice.
Page 28: EVM Method for POS
Similar procedure as SOP method, detailing specific differences.
Page 29: POS Example Steps
Introduction of a function (H) and relevant procedures explained.
Page 30: Logic Transformation Overview
Differentiating networks for simpler gate configurations.
Utilizing DeMorgan's Theorems for transformations.
Page 31: DeMorgan's Theorem - Formulation
Notation for NAND-NAND transformations based on principles discussed.
Page 32: DeMorgan's Theorem - Further Detailing
Best practice scenarios showcasing AND and OR transformations.
Page 33: NAND-NAND Transformation Example
Specific example of transforming an AND-OR network into NAND-NAND configuration.
Page 34: Example Continued
Analysis of the transformation into NAND-NAND structure and principles considered.
Page 35: NOR-NOR Transformation
Discussion around transforming an AND-OR network to NOR-NOR format.
Page 36: Example of NOR-NOR Transformation
Detailed breakdown of NOR-NOR transition on a functional network.
Page 37: General Rules for Transformation
Steps to adjust networks to specific NAND or NOR formats.
Page 38: Transformation Example: NAND-NAND
Description highlighting transformation approaches and level arrangements.
Page 39: Transformation Example: NOR-NOR
Detailed depiction showcasing transformation into NOR-NOR levels.
Page 40: Exercise on NAND-NAND Implementation
Task directed to apply NAND-NAND transformation without derivation processes.
Page 41: Exercise on NOR-NOR Implementation
Task focused on transforming a given function into a NOR-NOR configuration.
Page 42: Combinational Delay Explained
Explanation of the output delay in logic gates with input changes.
Page 43: Propagation Delay Clarification
Definition of propagation delay and measurements explained.
Page 44: Further Exploration of Propagation Delays
Discussion of delays in changing outputs and their recording methods.
Page 45: Introduction to Hazards and Glitches
Definitions and overview of hazards and glitches in electronic circuits.
Page 46: Hazards and Glitches Insights
The distinction between a hazard and a glitch based on circuit operation.
Page 47: Types of Hazards
Overview of static and dynamic hazards explaining their characteristics.
Page 48: Static Hazard Explanation
Detailed understanding of static hazards and their causes.
Page 49: Dynamic Hazard Overview
Definitions and examples showing how dynamic hazards manifest.
Page 50: Example of Hazard Analysis
Practical example illustrating hazards through function representation.
Page 51: Continued Example Analysis
Further breakdown of function demonstrating propagation through inputs.
Page 52: Complex Example Discussion
Discussion of possible transformations on more complex Boolean functions.