8085 Microprocessor Architecture and Interrupt System

Basic Microcomputer Architecture and Microprocessor Fundamentals

• Microprocessor Definition:

  • A microprocessor is the central controlling unit of a microcomputer, fabricated on a single small integrated circuit (IC) chip.

  • It is capable of performing Arithmetic Logic Unit (ALU) operations and communicating with other devices connected to it.

  • It consists of three primary components:

  • Arithmetic Logic Unit (ALU): Performs all arithmetic and logical operations on data received from memory or input devices.

  • Register Array: A set of internal storage registers identified by letters such as $B$, $C$, $D$, $E$, $H$, $L$, and the Accumulator ($A$).

  • Control Unit: Controls and coordinates the flow of data and instruction execution within the computer system.

• Operational Sequence of a Microprocessor:

  • Instructions are stored sequentially in system memory.

  • The microprocessor operates by continuously repeating a three-step cycle:

  1. Fetch: Retrieves the instruction code from the memory location.

  2. Decode: Interprets the fetched binary instruction to determine the required operation.

  3. Execute: Carries out the specified operation using internal registers and the ALU until a $STOP$ instruction is encountered.

  • Data processing workflow:

  • Registers store temporary data during processing.

  • The ALU performs computation functions.

  • Final computational results are transmitted in binary format to the output ports.

8085 System Bus Organization

• Bus Definition:

  • A bus is a collection of physical communication lines (wires) used to transmit information bits between various components organized within a microprocessor system.

• Types of System Buses:

  • Address Bus:

  • A collection of wires used to identify specific physical locations in main memory or peripheral devices.

  • Consists of $16$ individual lines designated as $A_0$ to $A_{15}$.

  • Directionality: Strictly unidirectional, flowing exclusively from the microprocessor out to input/output (I/O) devices and memory.

  • Addressing Capability: A $16$ -bit address bus allows the system to address up to $2^{16} = 65,536$ memory locations ($64\,\text{KB}$).

  • Data Bus:

  • A collection of wires through which data is transmitted between different functional blocks of the computer system.

  • Consists of $8$ individual lines designated as $D_0$ to $D_7$ .

  • Directionality: Fully bidirectional, allowing two-way data transfer between the microprocessor, main memory, and peripheral devices.

  • Transfers $8$ -bit binary information in parallel.

  • Control Bus:

  • A group of dedicated lines carrying timing, control, and synchronization signals generated by the CPU to manage peripheral devices.

  • Primary control signal pins on the 8085 microprocessor:

    • Input Output/Memory ($IO/\overline{M}$ )

    • Read control ($\overline{RD}$ )

    • Write control ($\overline{WR}$ )

  • Combining these three control signals allows the generation of four distinct system control signals:

    • Memory Read ($\overline{MEMR}$ )

    • Memory Write ($\overline{MEMW}$ )

    • Input Read ($\overline{IOR}$ )

    • Output Write ($\overline{IOW}$ )

Demultiplexing of the Address/Data Bus

• Multiplexed Address/Data Bus ($AD_0 - AD_7$):

  • To reduce the total pin count on the physical IC package, the lower-order address bus ($A_0 - A_7$) and the 8-bit data bus ($D_0 - D_7$) are combined into $8$ dual-purpose multiplexed lines designated as $AD_0$ to $AD_7$ .

  • During the first clock period (T-state) of a machine cycle, these lines carry the lower-order 8-bit address ($A_0 - A_7$).

  • During subsequent clock periods of the machine cycle, these lines function as the bidirectional data bus ($D_0 - D_7$).

• Demultiplexing Hardware and Circuitry:

  • To separate the lower-order address from data bits and prevent signal corruption, external demultiplexing hardware is required.

  • An external octal latch IC, specifically the 74LS373 Latch, is used to capture and hold the address.

  • Connection Setup:

  • The multiplexed bus lines $AD_0 - AD_7$ connect directly to the data inputs of the 74LS373 latch.

  • The Address Latch Enable ($ALE$) output signal from the 8085 is connected to the Enable pin ($G$) of the 74LS373 latch.

  • The Output Control ($\overline{OC}$) pin of the latch is permanently connected to ground ($V_{SS}$).

• Demultiplexing Operational Logic:

  • When $ALE$ is High (Logic 1): The latch becomes transparent. The lower-order address bits ($A_0 - A_7$) pass through the latch and are stored/latched on its output pins.

  • When $ALE$ goes Low (Logic 0): The latch freezes its output, preserving the lower-order address bits ($A_0 - A_7$) for the remainder of the cycle while freeing the lines $AD_0 - AD_7$ to operate as the bidirectional data bus ($D_0 - D_7$).

Generation of Control Signals

• Primary Control Signals Pin Functions:

  • $IO/\overline{M}$:

  • A status signal identifying whether the current memory cycle is addressed to I/O devices or memory.

  • Logic 1 (High): Address on the bus refers to an Input/Output device.

  • Logic 0 (Low): Address on the bus refers to Main Memory.

  • $\overline{RD}$:

  • Active-low signal controlling READ operations.

  • When logic 0, the selected memory location or I/O device is read by the MPU.

  • $\overline{WR}$:

  • Active-low signal controlling WRITE operations.

  • When logic 0, data currently on the data bus is written into the selected memory or I/O location.

• Decoder Hardware Setup (IC 74138):

  • A 3-to-8 line decoder (IC 74138) processes control signal logic.

  • Inputs to the decoder: $IO/\overline{M}$, $\overline{RD}$, and $\overline{WR}$.

  • Outputs from the decoder produce distinct active-low control commands:

  • $\overline{MEMR}$: Memory Read operation.

  • $\overline{MEMW}$: Memory Write operation.

  • $\overline{IOR}$: Input Read operation.

  • $\overline{IOW}$: Output Write operation.

• Control Pin Decoding Logic Table:

Internal Architecture of 8085 Microprocessor

• General Specifications:

  • Built using N-channel Metal-Oxide-Semiconductor (NMOS) technology.

  • Data Bus Width: $8$ bits (processes $8$ bits of data in parallel).

  • Address Bus Width: $16$ bits (can address $2^{16} = 65,536$ bytes or $64\,\text{KB}$ of memory space).

  • ALU Capacity: $8$-bit execution unit.

  • Operating Parameters: Requires a single $+5\,\text{V}$ DC power supply ($V_{CC}$) and operates with a standard clock cycle duration of $320\,\text{ns}$.

• Functional Internal Blocks:

  • Bus Architecture:

  • Address Bus: $16$ bits total, unidirectional.

  • Higher-Order Address Bus: Pins $A_8 - A_{15}$ (unidirectional).

  • Lower-Order Address/Data Bus: Pins $AD_0 - AD_7$ (multiplexed, bidirectional for data).

  • Arithmetic and Logic Unit (ALU):

  • Performs arithmetic operations: Addition, Subtraction, Increment, Decrement.

  • Performs logical operations: AND, OR, XOR, Complement, Compare, Rotate.

  • Timing and Control Unit:

  • Controls timing of all internal and external operations.

  • $X_1, X_2$: Crystal input connections for internal clock generator.

  • $\text{CLK OUT}$: Output clock signal for external system synchronization.

  • $ALE$: Address Latch Enable signal for demultiplexing $AD_0 - AD_7$ .

  • $\overline{RD}, \overline{WR}$: Active-low read and write control lines.

  • $IO/\overline{M}$: Selects I/O or memory operations.

  • $S_1, S_0$: Machine cycle status signals.

  • $\text{HOLD}, \text{HLDA}$: Bus request and acknowledge signals for Direct Memory Access (DMA).

  • $\text{READY}$: Bus wait-state control pin for synchronizing slow memory or peripheral devices.

  • Serial Input/Output Control:

  • Manages single-bit serial data transmission via two dedicated pins:

    • $\text{SID}$: Serial Input Data line.

    • $\text{SOD}$: Serial Output Data line.

  • Interrupt Control Block:

  • Manages hardware interrupt requests ($\text{TRAP}$, $\text{RST 7.5}$, $\text{RST 6.5}$, $\text{RST 5.5}$, $\text{INTR}$) and acknowledgement ($\overline{\text{INTA}}$).

  • Instruction Register and Decoder:

  • Holds the current instruction opcode fetched from memory and decodes it to execute required control operations.

8085 Register Organization

• Classification of Internal Registers:

  • 8-Bit Registers: Accumulator ($A$), Flag Register, $B$, $C$, $D$, $E$, $H$, $L$.

  • 16-Bit Registers: Program Counter ($\text{PC}$), Stack Pointer ($\text{SP}$).

  • 16-Bit Register Pairs: $BC$, $DE$, $HL$ (formed by pairing two 8-bit general-purpose registers).

  • Temporary Registers: $W$ and $Z$ (used internally by MPU; non-accessible to the programmer).

• Detailed Functionality of Registers:

  • Accumulator (Register A):

  • An $8$-bit register closely linked with the ALU.

  • Holds one of the operands for arithmetic/logical operations and receives the final output result of the operation.

  • General-Purpose Registers ($B, C, D, E, H, L$):

  • Six $8$-bit registers used by programmers to hold temporary data during instruction execution.

  • Can be grouped into $16$ -bit register pairs ($BC$, $DE$, $HL$) to store $16$-bit data or addresses.

  • The $HL$ register pair frequently functions as a memory pointer ($M$).

  • Program Counter (PC):

  • A $16$-bit register used to sequence program execution.

  • Contains the memory address of the next instruction byte to be fetched.

  • Automatically increments by 1 as each machine code byte is fetched from memory.

  • Stack Pointer (SP):

  • A $16$-bit register that acts as a memory pointer targeting a specific read/write memory area called the stack.

  • Automatically decremented by 2 during stack $PUSH$ operations and incremented by 2 during stack $POP$ operations.

8085 Flag Register Details

• Structure:

  • An $8$-bit special-purpose status register containing $5$ active flag bits (flip-flops).

  • The remaining $3$ bit positions are unassigned (vacant) and reserved for potential future processors.

  • Flags are set (Logic 1) or reset (Logic 0) based on the outcome of arithmetic and logical operations performed in the ALU.

• Bit Allocation and Specific Flag Descriptions:

• Sign Flag ($S$) [Bit 7]:

  • Reflects the value of the most significant bit (MSB / Bit 7) of the accumulator after an operation.

  • $S = 1$: Output result is negative.

  • $S = 0$: Output result is positive.

• Zero Flag ($Z$) [Bit 6]:

  • Indicates whether an operation generated a zero result.

  • $Z = 1$: The result in the accumulator is zero (all 8 bits are logic 0).

  • $Z = 0$: The result in the accumulator is non-zero.

• Auxiliary Carry Flag ($AC$) [Bit 4]:

  • Sets when a carry is generated by bit 3 ($D_3$) and passed to bit 4 ($D_4$) in arithmetic operations.

  • $AC = 1$: Auxiliary carry generated from bit 3 to bit 4.

  • $AC = 0$: No auxiliary carry generated.

  • Used internally for Binary Coded Decimal (BCD) operations.

  • Note: The $AC$ flag is the only flag register bit in the 8085 that is not directly accessible to the programmer via instructions.

• Parity Flag ($P$) [Bit 2]:

  • Tests the total number of logic 1s present in the accumulator.

  • $P = 1$: Even parity (accumulator contains an even number of 1 bits).

  • $P = 0$: Odd parity (accumulator contains an odd number of 1 bits).

• Carry Flag ($CY$) [Bit 0]:

  • Sets if an arithmetic operation generates a carry out of bit 7 (result exceeds 8 bits).

  • $CY = 1$: Carry bit generated.

  • $CY = 0$: No carry bit generated.

Detailed Pin Description of 8085 Microprocessor

• Complete Pin Assignments (Pins 1 to 40):

  • Pins 1 & 2 ($X_1, X_2$):

  • Crystal input connections.

  • An external crystal oscillator is connected across these pins to drive internal clock generation circuitry.

  • The input frequency is internally divided by 2. To operate the MPU at $3\,\text{MHz}$, a $6\,\text{MHz}$ crystal must be connected.

  • Pin 3 ($\text{RESET OUT}$):

  • Active-high output signal.

  • Used to reset external system components and peripheral ICs.

  • Driven high continuously as long as the $\overline{\text{RESET IN}}$ pin is held low.

  • Pin 4 ($\text{SOD}$):

  • Serial Output Data pin.

  • Transmits a single bit from the 8th position (MSB / bit 7) of the accumulator out to a serial device.

  • Controlled by executing the Set Interrupt Mask ($\text{SIM}$) instruction.

  • Pin 5 ($\text{SID}$):

  • Serial Input Data pin.

  • Accepts a single serial data bit and loads it into the 8th position (MSB / bit 7) of the accumulator.

  • Sampled by executing the Read Interrupt Mask ($\text{RIM}$) instruction.

  • Pin 6 ($\text{TRAP}$):

  • Non-maskable hardware interrupt.

  • Holds the highest execution priority among all interrupts.

  • Cannot be disabled by software instructions.

  • Triggering mechanism: Both edge and level triggered (signal must transition low-to-high and then remain high for a required duration).

  • Used for critical system conditions like emergency shutoff and power failure detection.

  • Pin 7 ($\text{RST 7.5}$):

  • Maskable hardware interrupt with 2nd highest priority.

  • Triggering mechanism: Positive edge triggered only (internal flip-flop latches on the rising edge of the signal).

  • Internal flip-flop remains set until cleared by a $\overline{\text{RESET IN}}$ signal or internal recognition.

  • Pin 8 ($\text{RST 6.5}$):

  • Maskable hardware interrupt with 3rd highest priority.

  • Triggering mechanism: Level triggered only (pin must be held high until recognized).

  • Enabled using the Enable Interrupts ($\text{EI}$) instruction and disabled using Disable Interrupts ($\text{DI}$).

  • Pin 9 ($\text{RST 5.5}$):

  • Maskable hardware interrupt with 4th highest priority.

  • Triggering mechanism: Level triggered (must be held high for a specific time period).

  • Operates similarly to $\text{RST 6.5}$.

  • Pin 10 ($\text{INTR}$):

  • Maskable hardware interrupt with the lowest priority.

  • Triggering mechanism: Level triggered.

  • General-purpose interrupt line; allows external hardware to vector the microprocessor to any subroutine location.

  • Pin 11 ($\overline{\text{INTA}}$):

  • Interrupt Acknowledge output signal.

  • Active-low signal sent by the microprocessor to indicate it has recognized an $\text{INTR}$ request.

  • Pins 12 - 19 ($AD_0 - AD_7$):

  • Dual-purpose multiplexed lower-order address/data lines.

  • Functions as lower address byte ($A_0 - A_7$) during T1 of a machine cycle, and as data lines ($D_0 - D_7$) during T2-T3 cycles.

  • Pin 20 ($V_{SS}$):

  • System ground connection ($0\,\text{V}$ reference).

  • Pins 21 - 28 ($A_8 - A_{15}$):

  • Higher-order address bus lines.

  • Unidirectional lines transmitting the upper address byte from MPU to memory.

  • Placed into high-impedance state (tri-stated) during $\text{HOLD}$ and $\text{RESET}$ modes.

  • Pins 29 & 33 ($S_0, S_1$):

  • Status pins indicating the current machine cycle operation in progress.

  • Pin 30 ($ALE$):

  • Address Latch Enable output.

  • Indicates whether $AD_0 - AD_7$ is presenting address or data bits.

  • $ALE = 1$: Bus serves as address bus ($A_0 - A_7$).

  • $ALE = 0$: Bus serves as data bus ($D_0 - D_7$).

  • Pin 31 ($\overline{\text{WR}}$):

  • Active-low Write control output signal.

  • Indicates that data on the data bus is to be written into the selected memory or I/O location.

  • Pin 32 ($\overline{\text{RD}}$):

  • Active-low Read control output signal.

  • Indicates that the selected memory or input device is to be read and data placed on the data bus.

  • Pin 34 ($IO/\overline{M}$):

  • Operation type selector output.

  • $IO/\overline{M} = 1$: I/O operation.

  • $IO/\overline{M} = 0$: Memory operation.

  • Pin 35 ($\text{READY}$):

  • Input signal used to synchronize slower peripherals with the fast MPU clock.

  • Logic 1: Peripheral is ready to transfer data.

  • Logic 0: Microprocessor enters wait states until $\text{READY}$ goes high.

  • Pin 36 ($\overline{\text{RESET IN}}$):

  • Active-low input signal.

  • Holding this pin low for at least 3 clock cycles forces the microprocessor to reset itself:

    • Program counter is set to $0000\text{H}$.

    • Control lines and buses are tri-stated.

  • Pin 37 ($\text{CLK OUT}$):

  • System clock output pin.

  • Provides a clock signal to drive other peripheral ICs in the system.

  • Pin 38 ($\text{HOLD}$):

  • Direct Memory Access (DMA) bus request input signal.

  • Logic high signals that an external controller (e.g., DMA controller) is requesting control of the address and data buses.

  • Upon receipt, the microprocessor completes the current machine cycle and relinquishes bus control.

  • Pin 39 ($\text{HLDA}$):

  • Hold Acknowledge output signal.

  • Driven high by the MPU to signal that it has acknowledged a $\text{HOLD}$ request and tri-stated its buses ($A_8-A_{15}$, $AD_0-AD_7$, $\overline{\text{RD}}$, $\overline{\text{WR}}$, $IO/\overline{M}$).

  • Bus ownership remains with the DMA controller until $\text{HOLD}$ is driven low, causing $\text{HLDA}$ to go low and returning bus control to the MPU.

  • Pin 40 ($V_{CC}$):

  • Power supply pin requiring a $+5\,\text{V}$ DC voltage source.

• Combined Bus and Status Encoding Table ($IO/\overline{M}$, $S_1, S_0$):

8085 Interrupt System

• Interrupt Concept & Execution Sequence:

  • An interrupt is a signal sent by an external device or initiated by software to alter or halt regular program execution.

  • Execution Sequence:

  1. The MPU receives an interrupt request signal while executing a main program.

  2. It completes execution of the current instruction.

  3. Program control branches to a specific interrupt subroutine (Interrupt Service Routine - ISR) by generating a $CALL$ signal.

  4. The microprocessor executes the ISR.

  5. Upon executing a $RET$ (Return) instruction at the end of the ISR, program control returns to the main program location where it was suspended.

• Hardware Interrupts:

  • Hardware interrupts are externally initiated signals received via physical input pins of the processor.

  • The 8085 contains 5 hardware interrupt pins:

  1. $\text{TRAP}$

  2. $\text{RST 7.5}$

  3. $\text{RST 6.5}$

  4. $\text{RST 5.5}$

  5. $\text{INTR}$

• Software Interrupts:

  • Software interrupts (also called Restart Interrupts) are explicit single-byte instructions (mnemonics/opcodes) inserted directly into a program.

  • The 8085 features 8 software instructions:

  • $\text{RST 0}$, $\text{RST 1}$, $\text{RST 2}$, $\text{RST 3}$, $\text{RST 4}$, $\text{RST 5}$, $\text{RST 6}$, $\text{RST 7}$

• Classification of Interrupts:

  • Maskable Interrupts:

  • Interrupts that can be delayed, disabled, or ignored by software execution ($\text{DI}$ instruction).

  • Includes: $\text{RST 7.5}$, $\text{RST 6.5}$, $\text{RST 5.5}$, and $\text{INTR}$.

  • Non-Maskable Interrupts:

  • Interrupts that cannot be disabled or ignored by the microprocessor.

  • Includes: $\text{TRAP}$ (used for critical emergencies like power failure).

  • Vectored Interrupts:

  • Interrupts where the execution subroutine starting address (vector location) is hardcoded internally.

  • Vector memory addresses are calculated using the general formula:       $\text{Vector Address} = 8 \times \text{TYPE}$       (Where TYPE is the restart index number, and the resulting decimal value is converted into Hexadecimal).

  • Non-Vectored Interrupts:

  • Interrupts without a predefined vector address.

  • The external peripheral device must supply the vector location address over the data bus during the interrupt acknowledge cycle.

  • $\text{INTR}$ is the only non-vectored hardware interrupt in the 8085.

• Hardware Interrupt Priority and Vector Locations:

• Software Interrupt Vector Locations:

Chapter Assignment Reference Questions

• Question 1: Draw Block Diagram of a Basic Microcomputer.

• Question 2: Draw and Explain Bus Organization of 8085 Microprocessor.

• Question 3: Explain De-multiplexing of Add/Data Bus. Write the function of ALE pin.

• Question 4: Explain how to Generate Control Signals using functions of control pins.

• Question 5: Draw and Explain 8085 Architecture.

• Question 6: Explain Register Organization of 8085.

• Question 7: Draw and Explain Flag Register of 8085.

• Question 8: Draw Pin Diagram of 8085. Explain function of each pin.

• Question 9: Explain types of Interrupts.

• Question 10: Write Interrupt Priority and Vector Locations of Interrupts.