Chapter 4: The Processor - Notes

Introduction

• CPU performance factors:
  • Instruction count: Determined by ISA and compiler.
  • CPI (Cycles Per Instruction) and Cycle time: Determined by CPU hardware.
• Two MIPS implementations will be examined:
  • A simplified version.
  • A more realistic pipelined version.
• Simple subset, showing most aspects:
  • Memory reference: lw, sw
  • Arithmetic/logical: add, sub, and, or, slt
  • Control transfer: beq, j

Instruction Execution

• PC (Program Counter) -> instruction memory, fetch instruction
• Register numbers -> register file, read registers
• Depending on instruction class:
  • Use ALU to calculate:
    • Arithmetic result
    • Memory address for load/store
    • Branch target address
  • Access data memory for load/store
• PC <- target address or PC + 4

CPU Overview

• Components:
  • Registers
  • ALU (Arithmetic Logic Unit)
  • Data Memory
  • Instruction Memory
  • PC (Program Counter)
• Connections and data flow between components.

Multiplexers

• Used to select one of several inputs as output

Control

• Control signals govern the operation of different components.

Logic Design Basics

• Information encoded in binary:
  • Low voltage = 0, High voltage = 1
  • One wire per bit
  • Multi-bit data encoded on multi-wire buses
• Combinational element:
  • Operate on data
  • Output is a function of input
• State (sequential) elements:
  • Store information

Combinational Elements

• AND-gate: $Y = A \&amp; B$
• Multiplexer: $Y = S ? I1 : I0$
• Adder: $Y = A + B$
• Arithmetic/Logic Unit: $Y = F(A, B)$

Sequential Elements

• Register:
  • Stores data in a circuit
  • Uses a clock signal to determine when to update the stored value
  • Edge-triggered: update when Clk changes from 0 to 1

Register with Write Control

• Only updates on clock edge when write control input is 1
• Used when stored value is required later

Clocking Methodology

• Combinational logic transforms data during clock cycles
• Between clock edges
• Input from state elements, output to state element
• Longest delay determines clock period

Building a Datapath

• Datapath:
  • Elements that process data and addresses in the CPU
  • Registers, ALUs, mux’s, memories, etc.
• MIPS datapath is built incrementally
• Refining the overview design

Instruction Fetch

• PC (Program Counter) provides the address to instruction memory.
• Instruction memory fetches the instruction.
• The instruction is passed on for further processing.
• PC is incremented by 4 for the next instruction (PC + 4).
• 32-bit register

R-Format Instructions

• Read two register operands
• Perform arithmetic/logical operation
• Write register result

Load/Store Instructions

• Read register operands
• Calculate address using 16-bit offset
• Use ALU, but sign-extend offset
• Load: Read memory and update register
• Store: Write register value to memory

Branch Instructions

• Read register operands
• Compare operands
• Use ALU, subtract and check Zero output
• Calculate target address
  • Sign-extend displacement
  • Shift left 2 places (word displacement)
  • Add to PC + 4 (already calculated by instruction fetch)

Branch Instructions - Datapath

• Shows the data flow for branch instructions.
• Includes reading registers, ALU operation, sign-extending the displacement, and calculating the branch target.

Composing the Elements

• First-cut data path does an instruction in one clock cycle
• Each datapath element can only do one function at a time
• Hence, we need separate instruction and data memories
• Use multiplexers where alternate data sources are used for different instructions

R-Type/Load/Store Datapath

• Diagram combining the data paths for R-type, load, and store instructions.
• Includes multiplexers for selecting the appropriate data sources.

Full Datapath

• Complete datapath diagram including instruction fetch, R-type, load/store, and branch instructions.
• Shows all necessary components and connections.

ALU Control

• ALU used for:
  • Load/Store: F = add
  • Branch: F = subtract
  • R-type: F depends on funct field
• ALU control functions:
  • 0000: AND
  • 0001: OR
  • 0010: add
  • 0110: subtract
  • 0111: set-on-less-than
  • 1100: NOR

ALU Control Details

• Assume 2-bit ALUOp derived from opcode
• Combinational logic derives ALU control
• Examples:
  • lw: ALUOp = 00, Function = XXXXXX, ALU function = add, ALU control = 0010
  • sw: ALUOp = 00, Function = XXXXXX, ALU function = add, ALU control = 0010
  • beq: ALUOp = 01, Function = XXXXXX, ALU function = subtract, ALU control = 0110
  • R-type: ALUOp = 10, Function = 100000 (add), ALU function = add, ALU control = 0010
• opcode always read and sign-extended and added, except for load write for R-type and load

The Main Control Unit

• Control signals derived from instruction opcode.
• Different instruction types (R-type, Load/Store, Branch) have different opcode formats.
• Control unit determines the appropriate control signals based on the opcode.

Datapath With Control

• Diagram showing the datapath with the main control unit and ALU control.
• Control signals govern the operation of various components.

R-Type Instruction with Control

• How control signals are set for R-type instructions.

Load Instruction with Control

• How control signals are set for load instructions.

Branch-on-Equal Instruction with Control

• How control signals are set for branch-on-equal instructions.

Implementing Jumps

• Jump uses word address
• Update PC with concatenation of:
  • Top 4 bits of old PC
  • 26-bit jump address
  • 00
• Need an extra control signal decoded from opcode

Datapath With Jumps Added

• Full datapath including jump instruction implementation.
• Includes additional multiplexer and control signal for jump instruction.

Performance Issues

• Longest delay determines clock period.
• Critical path: load instruction (Instruction memory -> register file -> ALU -> data memory -> register file).
• Not feasible to vary period for different instructions.
• Violates design principle: Making the common case fast.
• Performance is improved by pipelining.

Pipelining Analogy

• Pipelined laundry: overlapping execution.
• Parallelism improves performance.
• For four loads:
  • Speedup = $8/3.5 = 2.3$
• Non-stop:
  • Speedup = $2n/(0.5n + 1.5) \approx 4$ = number of stages

MIPS Pipeline

• Five stages, one step per stage:
  • IF: Instruction fetch from memory
  • ID: Instruction decode & register read
  • EX: Execute operation or calculate address
  • MEM: Access memory operand
  • WB: Write result back to register

Pipeline Performance

• Assume time for stages is:
  • 100ps for register read or write
  • 200ps for other stages
• Comparison of pipelined vs. single-cycle datapath (lw, sw, R-format, beq).

Pipeline Performance Visualization

• Illustrates the execution of instructions in a single-cycle datapath vs. a pipelined datapath.
• Shows the speedup achieved through pipelining.

Pipeline Speedup

• If all stages are balanced (i.e., all take the same time):
  • Time between instructionspipelined = Time between instructionsnonpipelined / Number of stages
• If not balanced, speedup is less.
• Speedup due to increased throughput; latency (time for each instruction) does not decrease.

Pipelining and ISA Design

• MIPS ISA designed for pipelining:
  • All instructions are 32-bits: Easier to fetch and decode in one cycle.
  • Few and regular instruction formats: Can decode and read registers in one step.
  • Load/store addressing: Can calculate address in 3rd stage, access memory in 4th stage.
  • Alignment of memory operands: Memory access takes only one cycle.

Hazards

• Situations that prevent starting the next instruction in the next cycle.
  • Structure hazards: A required resource is busy.
  • Data hazard: Need to wait for previous instruction to complete its data read/write.
  • Control hazard: Deciding on control action depends on previous instruction.

Structure Hazards

• Conflict for use of a resource
  • In MIPS pipeline with a single memory:
    • Load/store requires data access
    • Instruction fetch would have to stall for that cycle -> Causes a pipeline “bubble”
  • Pipelined datapaths require separate instruction/data memories or separate instruction/data caches

Data Hazards

• An instruction depends on completion of data access by a previous instruction
• Example:
  • add $s0, $t0, $t1
  • sub $t2, $s0, $t3

Forwarding (aka Bypassing)

• Use result when it is computed; don’t wait for it to be stored in a register
• Requires extra connections in the datapath

Load-Use Data Hazard

• Can’t always avoid stalls by forwarding; If value not computed when needed, it can’t forward backward in time!

Code Scheduling to Avoid Stalls

• Reorder code to avoid use of load result in the next instruction
• Example C code:
  • A = B + E;
  • C = B + F;
• Assembly code scheduling (with and without stalls).

Control Hazards

• Branch determines flow of control
• Fetching next instruction depends on branch outcome
• Pipeline can’t always fetch correct instruction
• Still working on ID stage of branch
• In MIPS pipeline, Need to compare registers and compute target early in the pipeline, and Add hardware to do it in ID stage

Stall on Branch

• Wait until branch outcome determined before fetching next instruction

Branch Prediction

• Longer pipelines can’t readily determine branch outcome early -> Stall penalty becomes unacceptable
• Predict outcome of branch, and Only stall if prediction is wrong
• In MIPS pipeline, Can predict branches not taken -> Fetch instruction after branch, with no delay

MIPS with Predict Not Taken

• Example illustrating branch prediction.
• Shows the pipeline stages for both correct and incorrect predictions.

More-Realistic Branch Prediction

• Static branch prediction:
  • Based on typical branch behavior
  • Example: loop and if-statement branches -> Predict backward branches taken -> Predict forward branches not taken
• Dynamic branch prediction:
  • Hardware measures actual branch behavior
  • Record recent history of each branch
  • Assume future behavior will continue the trend
  • When wrong, stall while re-fetching, and update history

Pipeline Summary

• Pipelining improves performance by increasing instruction throughput, and Executes multiple instructions in parallel; Each instruction has the same latency Subject to hazards: Structure, data, control
• Instruction set design affects complexity of pipeline implementation.

MIPS Pipelined Datapath

• Diagram of the MIPS pipelined datapath, highlighting the right-to-left flow that leads to hazards.

Pipeline Registers

• Need registers between stages to hold information produced in previous cycle

Pipeline Operation

• Cycle-by-cycle flow of instructions through the pipelined datapath
• “Single-clock-cycle” pipeline diagram: Shows pipeline usage in a single cycle, and Highlights resources used
• “Multi-clock-cycle” diagram: Graph of operation over time
• Diagrams for load & store are reviewed

IF for Load, Store

• Diagram illustrating the instruction fetch (IF) stage for load and store instructions in the pipelined datapath.

ID for Load, Store

• Diagram illustrating the instruction decode (ID) stage for load and store instructions.

EX for Load

• Diagram illustrating the execution (EX) stage for load instructions.

MEM for Load

• Diagram illustrating the memory access (MEM) stage for load instructions.

WB for Load

• Diagram illustrating the write-back (WB) stage for load instructions.

Corrected Datapath for Load

• Complete datapath diagram for load instructions, with corrections for pipelining.

EX for Store

• Diagram illustrating the execution (EX) stage for store instructions.

MEM for Store

• Diagram illustrating the memory access (MEM) stage for store instructions.

WB for Store

• Diagram illustrating the write-back (WB) stage for store instructions.

Multi-Cycle Pipeline Diagram

• Form showing resource usage

Multi-Cycle Pipeline Diagram

• Traditional form

Single-Cycle Pipeline Diagram

State of pipeline in a given cycle

Pipelined Control (Simplified)

• Simplified diagram of pipelined control.

Pipelined Control

• Control signals derived from instruction as in single-cycle implementation

Data Hazards in ALU Instructions

• sub $2, $1,$3
• and $12,$2,$5
• or $13,$6,$2
• add $14,$2,$2
• sw $15,100($2)
• Hazards are resolved with forwarding

Dependencies & Forwarding

Uses forwarding to resolve data dependencies.

Detecting the Need to Forward

• Pass register numbers along pipeline
• EX/MEM.RegisterRd = register number for Rd sitting in EX/MEM pipeline register
• ALU operand register numbers in EX stage are given by ID/EX.RegisterRs, ID/EX.RegisterRt
• Data hazards when:
  • 1a. EX/MEM.RegisterRd = ID/EX.RegisterRs
  • 1b. EX/MEM.RegisterRd = ID/EX.RegisterRt
  • 2a. MEM/WB.RegisterRd = ID/EX.RegisterRs
  • 2b. MEM/WB.RegisterRd = ID/EX.RegisterRt
    Fwd from EX/MEM pipeline reg; Fwd from MEM/WB pipeline reg

Detecting the Need to Forward (cont.)

• But only if forwarding instruction will write to a register!
  • EX/MEM.RegWrite, MEM/WB.RegWrite
• And only if Rd for that instruction is not $zero
  • EX/MEM.RegisterRd ≠ 0, MEM/WB.RegisterRd ≠ 0

Forwarding Paths

Diagram showing forwarding paths in the datapath.

Forwarding Conditions

• EX hazard:
  • if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10
  • if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10
• MEM hazard:
  • if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01
  • if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01

Double Data Hazard

*Consider the sequence:
* add $1,$1,$2
* add $1,$1,$3
* add $1,$1,$4

• Both hazards occur -> Want to use the most recent -> Revise MEM hazard condition -> Only fwd if EX hazard condition isn’t true

Revised Forwarding Condition

• MEM hazard:
  • if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01
  • if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01

Datapath with Forwarding

• Datapath diagram including forwarding logic.

Load-Use Data Hazard

Diagram illustrating a load-use data hazard.

Load-Use Hazard Detection

• Check when using instruction is decoded in ID stage
• ALU operand register numbers in ID stage are given by IF/ID.RegisterRs, IF/ID.RegisterRt
• Load-use hazard when:
  • ID/EX.MemRead and ((ID/EX.RegisterRt = IF/ID.RegisterRs) or (ID/EX.RegisterRt = IF/ID.RegisterRt))
    *If detected, stall and insert bubble

How to Stall the Pipeline

• Force control values in ID/EX register to 0 -> EX, MEM and WB do nop (no-operation)
• Prevent update of PC and IF/ID register -> Using instruction is decoded again -> Following instruction is fetched again
• 1-cycle stall allows MEM to read data for lw -> Can subsequently forward to EX stage

Stall/Bubble in the Pipeline

• Diagram illustrating a stall/bubble in the pipeline.

Stall/Bubble in the Pipeline (cont.)

• Alternative view of stall/bubble.

Datapath with Hazard Detection

• Datapath diagram including hazard detection unit.

Stalls and Performance

• Stalls reduce performance but are required to get correct results
• Compiler can arrange code to avoid hazards and stalls requires knowledge of the pipeline structure The BIG Picture

Branch Hazards

If branch outcome determined in MEM, these need to be flushed

Reducing Branch Delay

• Move hardware to determine outcome to ID stage:
  • Target address adder
  • Register comparator
• Example:
  • 36: sub $10, $4, $8
  • 40: beq $1, $3, 7
  • 44: and $12, $2, $5
  • 48: or $13, $2, $6
  • 52: add $14, $4, $2
  • 56: slt $15, $6, $7 ... 72: lw $4, 50($7)

Example: Branch Taken

• Illustration of what happens at the hardware level when taking a branch

Example: Branch Taken (cont.)

• A continuation of what happens at the hardware level when taking a branch

Data Hazards for Branches

• If register to compare is a destination for ALU instruction 2/3 instructions before the branch
  Can resolve using forwarding

Data Hazards for Branches

*If a comparison register is a destination of preceding ALU instruction or 2nd preceding load instruction, you need 1 stall cycle

Data Hazards for Branches

If a comparison register is a destination of immediately preceding load instruction need 2 stall cycles

Dynamic Branch Prediction

Deep pipelines and superscalar branch penalty is more significant Use dynamic predictionBranch prediction buffer - store outcome

1-Bit Predictor Shortcoming

Branches are Mispredicted twice, loops, etc.

2-Bit Predictor

Slightly better since you need 2 incorrect predictions before changing

Calculating the Branch Target

Predictor, still need to calculate the target address -
1 Target address cache/branch target buffer stores predicted target; indexed by PC of predicted instruction

Exceptions and Interrupts

Unexpected events, different ISAs use differeing terms

Handling Exceptions

*MIPS exceptions managed by System Control Coprocessor (CP0)
Save program counter to EPC and Save indication of the problem to Cause and jump to handler and 8000 00180

An Alternate Mechanism

Vectored interrupts - handler address determined by the cause and example is shown

Handler Actions

Read cause, transfer to relavant handler

Exceptions in a Pipeline

Another form of control hazard, prevent value from being clobbered and jump to handler

Pipeline with Exceptions

Instructions and pipeline

Exception Properties

Pipelining and restarting them

Exception Example

Exception on add in 40 sub $11, $2, $4 44and $12, $2, $5 48or $13, $2, $6

Exception Example

Sw bubble. …

Multiple Exceptions

Overlapping instructions; early instruction, etc.

Imprecise Exceptions

More simplification /manual completion

Instruction-Level Parallelism (ILP)

To increase ILP -> Deeper pipeline and Multiple issue

Multiple Issue

Static or Dynamic Multiple issue

Speculation