Lecture Material: Simple CPU Part 1

Lecture Material: Simple CPU Part 1

Basic Processing Unit

Reference: Hamacher CH 5 and CH 7.1-7.2

Copyright Notice

• Date: January 2026

• Authors: Donald Davis and T. Obuchowicz

• All rights reserved; no use permitted without prior consent.

Synchronous Machines

• Processor Operation

  • Based on the synchronous machine model.

  • Each state corresponds to a stage in an operation.

  • States determined by bits in registers and main memory (accessed via the bus).

• State Change

  • Triggered by appropriate input bits fed into the system.

  • Clock triggers (e.g., rising clock edge) are required for state changes.

  • Inputs alone do not cause a change in state due to the synchronous nature of the system.

• System Diagrams

  • Typically display control signals and hardware components (CPU, ALU, BUS, REGISTERS).

  • Clock signal usually implied but present for operations.

• Boolean Expression

  • Each operation linked to a logical AND with the clock pulse.

• Number of Bits for Commands

  • Number of bits defines the number of possible states.

  • Example: 16 bits allows for approximately $2^{16}$ different states, balanced by error states.

CPU Overview

• Control Unit Functions

  • Responsible for memory access (fetching words from memory) and instruction execution.

• Processor Complexity

  • Complexity based on internal architecture and capability to perform tasks.

• System Configuration

  • Simplified system using 8-bit registers for illustration.

Basic Processor Components

• Registers and ALU

  • Contains two registers: R0 and R1.

  • ALU includes TEMP register (input) and RESULT register (output).

• Bus

  • Single bus system governed by tri-state buffers.

  • Tri-state buffers control data flow, only allowing output when enabled (e.g., EN-R0 connects R0 to bus).

• Instruction Register (IR)

  • Instruction size set at 11 bits (max for this simple instruction set).

Basic Processor Operations

• Types of Commands

  • Four basic commands:

  • LOAD (op-code 10)

  • MOVE (op-code 11)

  • ADD (op-code 00)

  • SUBTRACT (op-code 01)

  • Requires 2 bits to encode commands.

• Instruction Format

  • For LOAD:

  • Format: OODDDDDDDDRd

    • O: Op-code bit,

    • D: Data bit,

    • Rd: Destination register bit (0 for R0, 1 for R1).

• Control Line Activation

  • Load immediate data requires active control line during rising clock pulse.

  • Example: LD-R0 for data in R0 or LD-R1 for data in R1.

  • IR-EN must be active to load immediate data onto the bus.

Handling Instructions and Control Signals

• Combinational Logic Requirement

  • Ensures appropriate control lines are active at correct times.

• Memory Access

  • Assumed to take one clock cycle (rising edge), but this may vary based on instruction complexity.

• Control Signal Generation

  • Uses combinational logic; a counter and decoder manage instruction sequencing.

  • Cycle sequence begins with loading IR data into control logic (T0).

LOAD Instruction Detailed Explanation

• Control Signal Combinations

  • For LOAD instruction (op-code 10):

  • If R0 is target: EN-IR and LD-R0 active.

  • If R1 is target: EN-IR and LD-R1 active.

• Boolean Expressions for Control Lines

  • Based on Rd value:

  • LD-R0 = NOT(Rd)

  • LD-R1 = Rd.

Advanced Boolean Control Mechanism

• Active Control Logic

  • Expression: $T1(IR-EN(LD-R0 + LD-R1))$

  • T1: Cycle controlled by counter.

  • IR-EN: Links IR data to bus.

  • LD-R0 and LD-R1 manage bus loading for registers R0 and R1, respectively.

• Timing Consideration

  • Load operation finalizes at the beginning of the next clock pulse, indicating the state transition timing.

MOVE Instruction Operation

• Instruction Details

  • MOVE instruction (op-code 11):

  • Source can be R0 or R1, and destination reflects the other register.

• Control Line Management

  • Source bit determines which EN signal to activate:

  • EN-R0 = NOT(Rs)

  • EN-R1 = Rs.

  • Destination bit determines which LD signal to activate:

  • LD-R0 = NOT(Rd)

  • LD-R1 = Rd.

ADD Instruction Flow

• Control Signal Overview

  • The ADD command (op-code 00) and its execution involve multiple cycles:

  • Cycle 1 (T1): Load source data into TEMP register of ALU.

  • Cycle 2 (T2): Load second ALU input and activate ADD control line.

  • Cycle 3 (T3): Transfer results back to destination register.

• Control Signal Activation Logic

  • Source bit controls input registers and TEMP register loading:

  • Expressions: EN-R0 = NOT(Rs), EN-R1 = Rs, LD-TEMP active.

  • Active control for the cycle: $T1((LD-TEMP)EN-R1 + (LD-TEMP)EN-R0)$.

Cycle T2 ADD Process

• Data Loading

  • ALU fed with second input from destination register, activating ADD control signal for calculation.

• Boolean Expression

  • Expression for active controls: $T2(ADD)(EN-R0 + EN-R1)(LD-RES)$.

  • Indicates shared data flow control through the bus.

Cycle T3 ADD Outcome

• Final Data Transfer

  • Results from ALU's RESULT register move to the specified destination register.

• Control of Destination Registers

  • Control lines loaded based on destination selected by instruction:

  • Expression: $T3((LD-R0)EN-RES + (LD-R1)EN-RES)$.

Timing and Delay Considerations

• Intrinsic Delays

  • Register load operations occur at the next rising clock edge (T4).

  • Activation of control lines incurs minor delays due to circuit dynamics.

Subtract Instruction Similarity

• Subtract Command Execution

  • Similar structure to the ADD command, except activating the SUB control line during T2 instead of ADD.

  • Boolean expression for controls mirrors that of the add command:

  • $T2(SUB)(EN-R0+EN-R1)(LD-RES)$.

Control Logic System Overview

• Instruction Register Information

  • OP-code indicates selected operation.

  • Execution determined by Boolean expressions and combinational logic.

• Active Conditions

  • Each control signal correlates with a specific set of operational conditions expressed as Boolean logic.

Control Signal Loading Mechanisms

• Loading Instruction Register

  • Process for each new instruction (first operation of the cycle):

  • Boolean expression: $LD-IR = T0$.

• Bus and Control Signals

  • Send IR data to register: $EN-IR = (T1)LOAD$.

  • ALU TEMP register loading needs $LD-TEMP = (T1)ADD + T1(SUB)$.

• Result and Register Loading

  • ALU result register loading requires $LD-RES = (T2)ADD + T2(SUB)$.

  • Specific register controls outlined:

  • $LD-R0 = (Rd')T3(ADD) + (Rd')T3(SUB) + (Rd')T1(LOAD) + (Rd')T1(MOVE)$.

  • $LD-R1 = (Rd)T3(ADD) + (Rd)T3(SUB) + (Rd)T1(LOAD) + (Rd)T1(MOVE)$.

Bus Loading Control Signals

• Register 0 and 1 Bus Control

  • $EN-R0 = (Rs')T1(ADD) + (Rd')T2(ADD) + (Rs')T1(SUB) + (Rd')T2(SUB) + (Rs')T1(MOVE)$.

  • $EN-R1 = (Rs)T1(ADD) + (Rd)T2(ADD) + (Rs)T1(SUB) + (Rd)T2(SUB) + (Rs)T1(MOVE)$.

• ALU Result Bus Control Signal

  • $EN-RES = T3(ADD) + T3(SUB)$.

• Counter Reset Control

  • Reset using $CLR-CNT = T3(ADD) + T3(SUB) + T1(LOAD) + T1(MOVE)$.

Control Logic Timing Governance

• Cycle Control

  • Governed by cycles (T0, T1, …) matching the processor clock sequence.

• Combinational Logic

  • Present in control logic circuits containing NOT inputs and direct source-destination data flow.

Next Lecture Preview

• Continued Investigation

  • The next lecture will expand on the basic processor concepts discussed in this session.