MSE4004 Topics for Exam III

  • Electronic device fabrication

    • Advanced lithography methods: why do we need them?

      • Shrinking feature sizes, increased density, improved performance, cost reduction

    • What are some of the methods and what mechanisms do they use?

      • EUV: short wavelengths → higher res and finer features (needed for semiconductor nodes)

      • Nanoimprint lithography → high res, photonics, nanoelectronics, and bioengineering

      • Electron Beam Lithography (EBL): EBL uses a focused beam of electrons to directly write patterns onto a substrate coated with an electron-sensitive resist material. It offers extremely high resolution

    • What equipment is necessary to use them? What kind of linewidths can be achieved?

      • EUV <10nm

      • Multiple Patterning <20

      • Nanoimprint Lithography (NIL) <10nm

      • Directed Self-Assembly (DSA): <10nm

      • Electron Beam Lithography (EBL): <10nm

    • Subtractive processing methods: Be familiar with most methods described in class, what are they used for, be able to tell which can be used for device fabrication, which you cannot (Lecture 7)

      • Wet chemical etching

        • Electrochemical → redox reactions

        • Isotropic etching (same rate in all directions, does not depend on orientation of mask)

        • Anisotropic etching (rate depends upon orientation to crystalline phases, used for complex shapes)

          • Etch rates are (100) > (110) > (111) for Si

          • (111) is the stop plane

        • Process

          • Transport of reactants to surface, surface reactions, transport of products from the surface

        • Used in micromachining

      • Dry chemical etching

        • Subtractive process that uses plasma (hot ionized gases) for removing materials

        • Dry etching can yield finer patterns than wet etching

        • This method is also safer as no corrosive acids or bases are needed

        • Glow discharge Methods or Ion Beam Methods

        • Pressures

          • Low: physical sputtering, unselective, directional, and can cause radiation damage

          • Medium: reactive ion etching, physical and chemical

          • High: plasma etching, faster, selective, least damage

        • Etching of efficiency is dependent on electron energy, density, ion energy and density, and current

        • Most common materials that are etched in processing IC’s: silicon, SiO, Ti, Al, Photoresist

        • RIE: Reactive Ion etching

        • Etched Copper can be done this way

        • Gas/Vapor Etching, Plasma Etching, Reactive Ion Etching (mostly nanofab), Sputter Etching

      • Sputter etching, ion milling

      • FIB

        • Used to carefully etch specific regions in a specimen

        • The ion column can be used for selective removal of material by ion beam milling.

        • The ion beam can also be used for ion-enhanced imaging of fine texture analysis in crystalline materials.

      • Laser Machining and EDM (electric discharge machining)

        • Laser: 

          • All classes of materials can be laser machined:

            • metals, ceramics, plastics

          • Energy determines the achieved temperature

        • EDM

          • Three types:wire,sinker and hole

          • Most common is wire EDM: Uses a wire to cause dielectric breakdown in air

          • Can be used for machining any conductive material

          • Yields excellent surface quality and very high accuracy

          • Procedure:

            • charge up an electrode

            • bring the electrode near a metal workpiece (oppositely charged).

            • as the two conductors get close enough a spark will arc across a dielectric fluid. This spark will "burn" a small hole in the electrode and workpiece.

            • 4. continue steps 1-3 until a hole the shape of the electrode is formed.

      • Types:

        • ICP (Inductive Coupled Plasma)

        • Electron Cyclotron Resonance (ECR)

        • Magnetic Confinement RIE

    • Similarities and differences between wet chemical etching and dry chemical etching, differences between different resist wall profiles

    • Electronic Packaging (Lecture 9)

      • Packaging Hierarchy for a PC Board

        • Packaging Levels:

          • Wafer level Packaging

          • Printed Wiring Board Level (PWB) or PCB

          • Packaging and Assembly

          • Sealing and Encapsulation

          • Thermal and Mechanical Reliability

        • Wafer Level Packaging (Individual Die)

          • Adhesives

          • Tab

          • Solder Bump

      • Single or Multichip Package

        • Multichip modules can be similar to single chip modules and have regular die attach, wire bonding and pin grid arrays

        • They can also be mounted by μBGA ball bump bonding as for single chip cases

      • Examples of substrates used Acronyms: SMT, PWB, MCM, TAB, PGA, BGA

        • Surface Mounted Technology (SMT)

        • Printed Wiring Board Level (PWB)

        • Multichip Module (MCM)

        • (TAB)

        • Pin Ball Grid Array (PGA)

        • Ball Grid Array (BGA)

        • Die Attach Film (DAF)

        • Dual In-line Package (DIP)

      • Die attachment methods

        • In the wire bond method (top), the die faces up and is attached to the package via wires.

        • The flip chip (bottom) faces down and is typically attached via μBGA solder bumps similar to the larger ones that attach BGA packages to the printed circuit board

      • Advantages of flip chip technology

        • Mounted upside down

        • Better connections to the chip as opposed to wire bonding where the wires add extra length, capacitance and inductance that limit signal speed.

        • More attachment points available since the whole area of the chip is available instead of just the edges

        • Faster production

        • Smaller overall package size

        • Uses μBGA

      • Current packaging schemes:

        • Surface mounted resistors, capacitors, inductors

        • Integrated resistors, capacitors, inductors

        • Cree/Wolfspeed - SiC single crystal substrates for GaN LEDs

        • Lumileds thin film flip chip → packaging of GaN LEDs

        • RF SAW filter SF16 → smallest as of August 2003

        • Kyocera

      • Thermal dissipation

        • As the number of transistors in each chip or integrated circuit increases, more heat needs to be dissipated

        • Methods used:

          • Through the substrate

          • Chip backside

        • Current thermal solution is sufficient for single chip, not acceptable for stacked high-performance chips

  • Differences between SOC and SOP

    • System on Chip VERSUS System on Package

    • SOP incorporates embedded components(resistors, capacitors, inductors) within the package rather than placing them on top

    • SOP ADV

      • Design simplicity

      •  Lower cost

      •  Higher system function integration

      •  Better electrical performance than SOC (system on a chip)

      •  Can stack different types of chips with processors and flash memory .

    • SOC → ability to place multiple function "systems" on a single silicon chip, cutting

    • development cycle while increasing product functionality, performance and quality.

  • Nanoelectronics (Lecture 8)

    • What determines whether a device is a nanoelectronic device or not?

      •  Can be made from:

        • Individual nanoparticles, nanorods, nanotubes,etc..

        • Make contacts using photolithography patterns or soft lithography

        • Mixing with polymers or other materials

      • Most made by sol-gel

    • What are some examples of nanoelectronic devices?

      • Applications include: single electron transistors, chemical and mechanical sensors, and components for solar cells, displays, etc.

    • What materials are currently being used?

      • CdSE Nanocrystals - quantum dots (demonstrate quantum confinement or size effects)

      • Electrochromic Polymers

    • Know the differences between graphite, graphene, graphene oxide, reduced graphene oxide, C60 , nanotubes, nanowires, nanobelts

      • Graphite: carbon hexagonal lattice, good conductor

      • Graphene: single layer carbon in 2D honeycomb lattice

      • Graphene Oxide: graphene with oxygen functional groups

      • Reduced Graphene Oxide: Graphene oxide with additional electrons (removed some oxygen functional groups)

      • C60: Buckyball

      • Nanotubes: cylinders of rolled up graphene sheets

      • Nanowires:1D Carbon in linear fashion

      • Nanobelts:narrow, belt like structures of carbon in ring like configuration

    • What methods are normally used to characterize nanomaterials?

      • SEM, TEM, AFM, XRD, Raman Spec, FTIR

    • Why is there an emphasis on transparent conductors?

      • Touchscreens and displays,

      • Solarcells and photovoltaics

      • LEDs and windows

    • Why is there emphasis on flexible electronics?

      • Form Factor Flexibility (Durability), Wearables, Energy Storage, Space saving

  • Point defects in materials (Lecture 11)

    • Defect types

      • Point defects (vacancies, interstitial and substitutional)

      • Line Defects (dislocations)

      • Area Defects (Grain Boundaries)


  • Electronic Defects (0D)

  • Point Defects (0D)

  • Line Defects (1D)

  • Planar Defects (2D)

  • Dislocations Loops (2D & 3D)

  • Grain Boundaries (2D & 3D)

  • Clusters (3D)

  • Kroger-Vink notation

    • ESC

    • E represents what is on the site, either V for a vacancy or, if occupied by an element, the element symbol

    • S represents what type of site is occupied by E, either i for an interstitial or, if normally occupied by an element, the symbol for that element

    • C represents the charge relative to the normal ion charge on the site S, using dots to represent positive relative charges, primes to indicate negative relative charges, and X to indicate zero relative charge

  • Mass action relations and how to determine equilibrium constants for different defect reactions

    • Mass balance: can’t create or destroy matter in a reaction to form defect (i.e., mass on the left side of the equation equals that on the right)

    • Site balance: sites must appear in correct ratio for the stoichiometric crystal on either side of reaction.

    • Charge balance: crystal must always be electrically neutral (net charge on the left side of the equation equals that on the right)

  • Low partial pressure of oxygen & High partial pressure of oxygen

    • Separate into regimes 

  • Brouwer diagrams

    • Constructing Brouwer Diagrams (as a function of PO2 or similar) requires the meticulous following of several steps.

    • 1. Write all the defect reactions expected in the system with their corresponding equilibrium constant equation.

    • 2. Write the electroneutrality equation.

    • 3. Separate the problem into regimes and write the corresponding Brouwer approximation equation for each case.

    • 4. Cleverly combine the equations in step 3 with the equations in step 1 to solve for each of the defect concentrations and establish their PO2 (or similar) dependence (slopes in the diagram) in each region.

    • 5. Substitute values of K’s (if known) and obtain concentration values for each defect in each regime (if possible).

    • 6. Find the PO2 (or similar) value for the boundaries between two regions.

    • 7. Neatly plot your diagram based on the calculated values from steps 4-6

  • Effect of defects on electrical conductivity and dominant charge carriers

    • Mixed Conductors (SrTiO3)

    • Ionic Conductors (CeO2)

    • Acceptor Doping (ZrO2)

  • Temperature dependence behavior for different types of materials, especially how ionic conductors differ from semiconductors and highly conducting materials and what determines their activation energy

  • Choose at least two other group term paper topics and be able to summarize what you learned from them 

    • Magnetic Levitation

    • Lithium batteries

    • Carbon Capture