CPE201 Digital Design Class 12 Notes

The Rest of the Semester

• Key Topics
  • Combinational Logic
  • More Complex Circuits:
  • Adders
  • Flip-Flops
  • Shift Registers
  • Counters
  • Design Examples
  • More Debugging
  • Topics for Future Semesters

Outline

• Karnaugh Maps and SOP (Sum of Products)
• Karnaugh Maps and POS (Product of Sums)
• Don't Care Condition
• 7 Segment Displays

SOP Minimization

• Process of minimizing SOP expressions:
  • 3 Input Variables:
  • 1 cell = 3 input product term
  • 2 cells = 2 input product term
  • 4 cells = 1 input product term
  • 8 cells = All terms true, F=1
  • 4 Input Variables:
  • 1 cell = 4 input product term
  • 2 cells = 3 input product term
  • 4 cells = 2 input product term
  • 8 cells = 1 input product term
  • 16 cells = All terms true, F=1

Example for SOP Minimization

• Expression:
  • $B' + A'B + ABC'$
• Groups:
  • 3 groups of 4 cells
• Simplified Result:
  • $A' + B' + C'$

Another Example

• Expression to Minimize:
  • $AB + AC' + A'BC$
  • $ABC' + BC' + D$

Don't Care Condition

• Definition:
  • For conditions that cannot occur.
• Purpose:
  • Further simplification of logic expressions.

Karnaugh Maps and POS

• Similar to SOP but focuses on 0’s:
• Write all simplified terms as POS terms.

Example for POS

• Expression:
  • $(A + B + C')(A + B' + C')(A' + B')(A' + B + C)$$

Conversion Methodology

• Process for filling in Karnaugh Maps:
  • Translate truth tables into Karnaugh Maps
  • Group other truth values
  • Write out corresponding terms

Minterms and Maxterms

• Definition:
  • Minterms: Inputs yielding 1 on the truth table.
  • Maxterms: Inputs yielding 0 on the truth table.

Example of Minterms and Maxterms

7-Segment Displays

• Segment Arrangement:
  • Displays digits 0-9 and certain letters.
  • Specific segments active for each digit.

Active Segments for Hex Digits

Logic for Active Segments of Display

• For segment ‘a’:
  • Active for digits: 0, 2, 3, 5, 6, 7, 8, 9, A, C, E, F
• Boolean expression can be expressed using logic variables H (Hex):
  • $H2'H1'H0' + H3H1'H0' + H3H2'H1' + H3'H2H0' + H3'H1 + H2H1 + H1H0'$

Lecture Reading

• Current Lecture:
  • Section 4.9 (Karnaugh Map SOP Minimization)
  • Section 4.10 (Karnaugh Map POS Minimization) - Chapter 4 Applied Logic
• Next Lecture Topics:
  • Section 6.1 (Half and Full Adders)
  • Section 6.2 (Parallel Binary Adders)
  • Section 6.3 (Ripple Carry and Look-Ahead Carry Adders)