Microfabrication Notes

Chapter 2: First-Pass Introduction to Microfabrication

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MEMS fabrication represents a paradigm shift from traditional machining processes like milling, lathing, polishing, joining, and welding.
It requires understanding the unique features and limitations of integrated circuit (IC) fabrication.
The portfolio of MEMS fabrication techniques is rapidly expanding, aiming to:
- Increase the variety of materials involved.
- Increase fabrication efficiency.
- Reduce manufacturing costs.

2.1 Overview of Microfabrication

MEMS and IC devices are generally made on single crystal silicon wafers.
Wafer process steps:
- Molten silicon
- Crystal seed
- Mechanical draw
- Crystal rod
- Sawing
- Polishing
- Dicing
- Die
- Packaging
- Bonding wires
- Chip pins
Bulk silicon with crystalline consistency does not exist in nature and needs to be prepared through industrial processes.
Process to make bulk crystal silicon:
- Start with a perfect single crystal silicon seed.
- Dip it into a molten silicon pool.
- Slowly draw it out of the liquid.
- Silicon crystallizes, forming rods with consistent crystallinity.
- Rods are sawed into thin, circular slices (wafers) and polished.
Wafers undergo a multi-step fabrication process in a clean room environment.
Cleanliness of air in a clean room is classified according to the concentration of air-borne particles (with sizes larger than $0.5 \,\text{mm}$ .
Cleanroom classification:
- Class 1: Fewer than 1 particle per $ft^3$ of air.
- Class 100: Fewer than 100 particles per $ft^3$ of air.
- Average outdoor air contains more than 400,000 particles per $ft^3$ .
Cleanroom class vs. production resolution capability:
- Class 1000: Production down to approximately $4 \,\text{mm}$
- Class 100: Production down to approximately $1.25 \,\text{mm}$
- Class 10: Production down to approximately $0.7 \,\text{mm}$
- Class 1: Production down to approximately $0.3 \,\text{mm}$
- Class 0.1: Production down to approximately <0.1 \,\text{mm}
State-of-the-art integrated circuits have used linewidths smaller than $0.18 \,\text{mm}$ since 1999.
Water and chemical solutions must go through stringent, costly manufacturing and conditioning processes.
Ions in water (e.g., sodium ions) can migrate into silicon and thin film materials, becoming trapped charges in dielectrics and hurting device performance.
De-ionized water used in semiconductor manufacturing has resistivity in excess of $18 \,\text{MΩ}$ , compared to less than $50 \,\text{kΩ}$ for tap water.
Precision patterns are made using photolithographic patterning method.
Collimated light passes through a mask and an image-reduction lens before hitting the wafer.
This process is akin to taking a photograph of an object through a telephoto lens and recording the image on a photosensitive film.
Higher energy light (smaller wavelength) produces smaller linewidths; resolution is dictated by the diffraction limit.
Using a machine-automated photolithography process called step-and-repeat, many identical units can be made on a same wafer with high linewidth resolution ( $0.1$ \text{mm} or smaller in commercial processes).
The machine used for performing the step-and-repeat process is called a stepper.
After a reduced image of the mask is printed to an area on a wafer, the wafer is translated by a precise distance, and another exposure is made.
Many identical devices, called dies, are made on one given wafer in a single pass.
Dies per wafer approximation:
- 2" wafer: ~21 dies (1 x 1 cm
- 4" wafer: ~82 dies
- 6" wafer: ~178 dies
- 8" wafer: ~314 dies
- 10" wafer: ~770 dies
Larger wafers offer economy of scale, but upgrading wafer sizes requires significant investment (tens of millions of US dollars) for equipment.
Only large volume products warrant the full benefits of larger wafers. For small volume products, the parallel fabrication benefit is offset by setup costs/high-resolution masks.
Dies have spacings between them so they can be mechanically cut and separated into chips.
Each cut die (chip) is electrically connected and encapsulated for commercial resale.
Packaging is incorporating a loose die into a housing and a system.
Process yield is the percentage of dies with satisfactory performance, deeply affecting fabrication economy and device cost.
Yield is influenced by design, materials, and processes; yield figures are closely guarded secrets in industry.
Key differences between MEMS and macroscale machining:
1. Silicon is mechanically brittle and cannot be shaped by cutting tools.
2. MEMS are made on planar crystalline wafers to ensure consistent focus distance during lithography and identical crystal orientation.
3. Loose dies are too small and numerous to be handled by human labor and must be compatible with automated sorting and pick-and-place machines.
A chip is placed into a package, which is then mounted on a circuit board.
Smart phones contain many components including display, battery, computer chip, camera, and sensors (e.g., inclination, motion, microphone, touch screen).
A microphone chip includes a package casing with the diced silicon die mechanically mounted and electrically connected by bonding wires.
Various integration methods exist for combining mechanical elements with circuitry.
This book focuses on the process flow between a bare wafer and an undiced wafer with fabricated devices.
Understanding about the packaging schemes is important for a MEMS developer.

2.2 Essential Overview of Frequently Used Microfabrication Processes

Microfabrication involves many processes and techniques, including their physics and chemistry, behavior under various conditions, applications, recipes, equipment, and operation.
Processes are categorized as additive, subtractive, patterning, material modification, and mechanical steps.

2.2.1 Photolithography

The goal is to produce fine features on wafer surfaces by depositing photo-sensitive chemicals (photoresists) on a wafer, exposing it with light through a mask, and removing photoresist material modified by light.
The starting point of a lithography process is to coat a wafer with photoresist through spin coating.
A wafer is held on a rotating stage.
Photoresist is applied to the center of the wafer at rest position.
The wafer is then spun at high speed, causing the photoresist to move towards the edge of the wafer under centrifugal forces.
After the wafer spinning is stopped, a uniform thin layer of photoresist is coated on the front surface of a wafer.
Process variables include the wafer spinning speed, the viscosity of the resist, and the types of resists (e.g., target wavelength, sensitivity).
Typical thickness of photoresist is generally 1–10 mm.
Lithography patterning procedure:
- A wafer is first covered with a uniform thin layer of resist (step a).
- A mask, consisting of a transparent substrate (e.g., glass or quartz) with opaque features, are brought close to the resist-coated wafer (step b).
- High energy, collimated light rays strikes the mask-wafer assembly.
- Resist regions that are not covered by opaque features are exposed, changing the chemical composition of the resist.
- For positive resist, the exposure by light causes the resist to be more soluble in a wet chemical developer (step c).
- This allows the opaque features on the mask to be faithfully transferred to the wafer (step d).
A pattern in photoresist can be further transferred to an underlying layer, using the photoresist as a mask layer.

2.2.2 Thin Film Deposition

Functional materials, conductors and insulators can be incorporated on a wafer through additive deposition processes.
One method is transferring material directly from a source to the wafer surface atom-by-atom (e.g., metal evaporation, metal sputtering).
The process is generally conducted in a low-pressure environment.
A wafer and a metal source are both placed inside a vacuum jar.
The metal can be transferred either by heating it (evaporation) or by bombarding it with high-energy ions (sputtering).
The achieved thickness is proportional to the power and time.
A second method for placing thin film materials on a wafer surface is chemical vapor deposition.
Active species arrive at the wafer surface, react under favorable conditions (heat or plasma), and produce a solid phase absorbed onto the wafer.
Byproducts are removed, and continuous reaction builds a material layer on the wafer surface.
Typically the average thickness of thin film deposited by CVD, evaporation or sputtering is below 1 mm.
To deposit films of greater thickness is typically too time consuming or impractical.

2.2.3 Thermal Oxidation of Silicon

Silicon dioxide is an important insulating layer and a method of forming a high-quality layer is by reacting silicon wafers with oxygen atoms at high temperatures (>900°C).
Wafers are placed inside a heated quartz tube.
A layer of oxide forms, separating the interior silicon from oxygen atoms, which must diffuse through the oxide to react with fresh silicon on the inner interfaces.
As the oxide layer grows, the oxidation rate decreases.
The deposition rate and ultimate thickness depend on temperature; thermal oxide thickness is typically below $1.5 \,\text{mm}$ .

2.2.4 Wet Etching

Removing materials by wet chemical reaction is common and used for metals, dielectrics, semiconductors, polymers, and functional materials.
The selectivity of etching against masking materials, substrates, and the target material is crucial.
Important performance characteristics include etch rate, temperature, and uniformity.
If a film with starting thickness $t{f0}$ is covered by a masking material with initial thickness $t{m0}$ , and exposed to an etchant, then:
- The thickness of the film becomes $tf$ , and the thickness of the mask becomes $tm$ . Here and
- $t{m0} - tm = t \cdot \text{etch-rate-on-mask}$ .
- $t{f0} - tf = t \cdot \text{etch-rate-on-film}$ .
Ideally, the etch rate on the film should be much greater than that on the mask.
Etch rate on film in windows of different sizes may differ, due to the so called “loading effects”.
At the end point of the process ( $t_e$ ), the films in both windows should be completely removed, whereas the thickness of the mask may be reduced to
$tm = t{m0} - t_e \cdot \text{etch-rate-on-mask}$ .
While the etch rate is defined in the vertical direction, an etchant may well attack the lateral walls of the thin film.
The extent of the lateral etch during time $t_e$ is called undercut.
The amount of undercut affects the precision of the pattern transfer process.

2.2.5 Silicon Anisotropic Etching

Anisotropic etching of silicon is a micromechanical process used to produce three-dimensional structures.

2.2.6 Plasma Etching and Reactive Ion Etching

Plasma etching is a method of removing materials without wet chemicals (dry etching).
It is carried out in a plasma etcher, where a chamber with two opposing electrodes is filled with a chemically active gas.
The process pressure is typically low (perhaps 1/2000th of atmospheric pressure).
Gas species are broken up by the electric field, creating electrically charged active gaseous radicals.
Radicals may react with the wafer chemically or be accelerated to high speed to interact with materials physically (bombardment, sputtering).
Physical etching is more directional and anisotropic, whereas chemical etching is isotropic and material selective.
If the electrode holding the wafer is grounded, the etching is called plasma etching.
If the wafer is fixed to an electrode on which AC bias is applied, the etching is called reactive ion etching.
Reactive ion etching is more physical and its etch rate distribution is more anisotropic.
Deep reactive ion etching (DRIE) produces deep trenches with vertical, smooth sidewalls in silicon.

2.2.7 Doping

Doping is planting dopant atoms into the host semiconductor lattice to change its electrical characteristics.
Dopants can be placed on the surface or injected using ion implantation, then diffused from high- to low-concentration regions under thermal activation.
The desired shape of the resistor is shown in the top-most figure. The resistor feature should be moderately doped (with concentration ranging from $10^{15}$ to $10^{18} \,\text{cm}^{-3}$ ).
The two ends of the resistor should have higher doping concentration, on the order of $10^{19}$ to $10^{20} \,\text{cm}^{-3}$ , in order to form ohmic contacts with metal leads.
A mask shield is first deposited in step a and patterned to form windows.
The wafer is exposed to a source of dopant, which can not penetrate the mask shield layer but can enter the silicon via the open windows.
The arms of the resistor are then patterned (in step b) for performing a lower dose doping.
Finally, metal leads are deposited and patterned to connect with the resistor (step c).
Dopant atoms perform random walk (Brownian motion) in a semiconductor lattice under elevated wafer temperature.
Overall population of dopant atoms moves from high-concentration to low-concentration ones is called thermal diffusion.
Dopant diffusion in silicon follows Fick’s law:
$\frac{0C(x,t)}{0t} = - \frac{0J(x,t)}{0x} = \frac{0}{0x} \Bigg(D \frac{0C(x,t)}{0x} \Bigg),$
where $J(x, t)$ is the flux of dopant per unit area at location $x$ and time $t$ , and $D$ is the diffusivity of dopants.
Diffusivity depends on temperature:
$D = D0 \exp \Bigg(-\frac{E}{kT}\Bigg).$ where $D0$ is a reference factor, $E$ the activation energy, $T$ the temperature, and $k$ the Boltzmann constant.
For boron and phosphorus in single crystal silicon:
- Boron: $D_0 = 0.76 \,\text{cm}^2/s$ , $E = 3.46 \,\text{eV}$ .
- Phosphorus: $D_0 = 3.85 \,\text{cm}^2/s$ , $E = 3.66 \,\text{eV}$ .
Solution to Fick's law:
$C(x, t) = C_s \text{erfc} \Bigg( \frac{x}{2 \sqrt{Dt}} \Bigg),$
The reduction of substrate temperature during the diffusion process can drastically decrease the diffusivity and the spatial extent of dopant spreading.
Key considerations:
1. Doping can only be performed on top surfaces of wafers.
2. High temperature during later steps can cause dopant redistribution and changes of electrical characteristics.

2.2.8 Wafer Dicing

A wafer consists of multiple dies, each must be broken into separate pieces before being packaged individually.
Dies are separated by dicing, using a high-speed rotating saw blade to cut trenches in silicon wafers.
The cutting process produces particles, and water is sprayed to lubricate and remove heat.
The thinned trenches allow silicon to be broken off easily without fracturing.
This can damage freestanding MEMS mechanical components.
Laser ablation has also been used to dice wafers in lieu of dicing saw.
Laser stealth dicing creates internal modified lines invisible on the surface.

2.2.9 Wafer Bonding

Wafer-to-wafer bonding joins wafers with disparate materials, surface profiles, and functional characteristics to form unique structures.
It involves bringing two wafers close with proper spatial alignment to form permanent bonding under proper physical and chemical conditions.
Wafer bonding can be performed using a variety of materials and temperature conditions.
Wafer bonding can be aided through interfacial layers of thin films deposited on the wafer surfaces.
Bonding processes are categorized by temperature: room temperature, low-temperature ( $<100°C$ ), and high-temperature ( $>100°C$ ).
Wafer bonding can be direct (without adhesive) or indirect (with an adhesion layer).
Bonding can be initiated by mechanical contact force, molecular attractive force, or electrostatic force.
Wafers can be chemically or mechanically modified after bonding (e.g., thinned by polishing or etching).
Wafer transfer planarizes surfaces and produces devices such as mirrors and membranes.
Most bonding operations are conducted at the wafer scale; however, bonding can be performed at die or device level.

2.3 The Microelectronics Fabrication Process Flow

Understanding IC fabrication is necessary to grasp micromachining processes.
Fabrication involves deposition, removal, and patterning.
A generic process for a field effect transistor (FET) involves repeating deposition-lithography-etching cycles.

2.4 Silicon-Based MEMS Processes

MEMS devices were first developed on silicon wafers due to mature processing technologies and expertise.
Silicon comes in three forms:
- Single crystal silicon.
- Polycrystalline silicon.
- Amorphous silicon.
Single crystal silicon has a regularly organized crystal lattice throughout the bulk found in:
1. Single crystal silicon wafers grown from a high-temperature melt/recrystalization process.
2. Epitaxially grown silicon thin films.
3. Single crystal silicon obtained from recrystalizing polycrystalline or amorphous silicon by global or local heat treatment.
Polycrystalline silicon is made of multiple crystalline domains with different crystal orientations; domain walls (grain boundaries) affect electrical conductivity, mechanical stiffness, and chemical etching.
Polysilicon is grown by low pressure chemical vapor deposition (LPCVD) or by recrystalizing amorphous silicon through global or local heat treatment.
Amorphous silicon exhibits no crystalline regularity, and is deposited by CVD at lower temperatures than polysilicon.
The transition temperature above which polycrystalline structure forms during deposition is $580°C$ .
Two fundamental classes of fabrication technologies are bulk micromachining and surface micromachining.
Bulk micromachining selectively removes bulk material to form 3D features.
It may be combined with wafer bonding to create more complex structures.
Example: Micromachined pressure sensor fabrication involves:
* A bottom wafer etched to form a cavity
* A top wafer to make the membrane
A combined mechanical wash and oxidizing acid bath may be used, followed by a rinse by ultrapure water.
The cleaned wafer is placed inside a high-temperature furnace filled with running oxygen gas or water vapor. Oxygen atoms present in the air or dissociated from the water molecule will react with silicon to form a protective silicon dioxide thin film.
The wafer is removed from the furnace and cooled to room temperature. It will be very clean, because any organic molecules would have been decomposed in the high-temperature oxidation step. A layer of thin film photoresist is deposited on the front surface of the wafer.
(A chemical called hexamethyldisilazane, or HDMS, is sometimes spin- or vapor-coated to help increase the adhesion between the photoresist and an oxide surface.) The photoresist is typically spin coated. Alternatively, photoresist thin film can be deposited by vapor coating, mist coating, or electroplating [26].
The wafer is baked in a convection oven to remove some portion of the solvent from the photoresist (PR) layer to establish firmness. This step is generally called “soft bake”.
The photoresist is exposed through a mask with a high-energy radiation (such as ultraviolet ray, electron beam, or X-ray).
Entire wafer is placed inside a developing solution (often called developer) that removes loosely bound photosensitive polymer.
Photoresist needs to be baked again, this time at a higher temperature and often for a longer duration than the soft bake.
This second baking step, called “hard bake”, removes remaining solvents and makes photoresist that remains on the wafer stick to the wafer even stronger
The photoresist mask is here used to selectively mask the underlying layer, the silicon oxide, against a hydrofluoric acid etchant bath.
A HF etchant attacks oxide within the exposed window, but has negligible etch rate on the underlying silicon and the photoresist mask.
The photoresist is removed using an organic solvent etchant such as acetone (at room temperature or elevated temperatures).
The silicon wafer is immersed in a wet silicon etchant, which does not attack the silicon oxide.
Wafer is tilted to provide a clear view of the through-wafer cavity.
A second silicon wafer is firmly bond to the frontside of the bottom wafer processed through step (g).
The bonded top wafer is thinned by using mechanical polishing or chemical etching. The remaining thickness of the top wafer determines the thickness of the membrane. Thin membranes are desired to have high sensitivity.
Strain sensors are then made on the prepared membrane.
A thin film layer (e.g., oxide) is deposited and patterned. It serves as a barrier layer to ion implantation. Areas on the silicon wafer hit directly by energetic dopant ions will become doped and form a piezoresistor, which changes its resistance upon applied stress due to membrane bending under pressure difference.
Different materials yield unique performance characteristics.
Surface micromachining creates free-standing mechanical elements by removing an underlying place-holding thin film layer (sacrificial layer).
The sacrificial layer is deposited and patterned, followed by a structural layer on top.
Then, the sacrificial material is selectively removed to free the structural layer on top.
Increasingly, bulk and surface micromachining are combined to create complex structures, along with wafer bonding, laser machining, micromolding, and 3D assembly.

2.5 Packaging and Integration

Integration combines mechanical and electrical functionalities; packaging places diced chips into modules for circuit board assembly.
Packaging includes dicing, die assembly, encapsulation, and testing.
Packaging is crucial for MEMS device design, often accounting for 30–90% of the finished system cost.

2.5.1 Integration Options

Circuits and mechanical elements can be co-fabricated monolithically on the same silicon die.
Circuits can be integrated with MEMS devices at the wafer level, package level, or board level.
Wafer-level integration places micromechanical components and circuits on the same wafer:
* Side-by-side
* Top-bottom
Monolithic integration approaches:
1. Post-processing: Micromechanical elements fabricated on top of a wafer with existing circuits.
2. Pre-processing: Micromechanical elements fabricated first, followed by IC fabrication.
3. Side-by-side: Micromechanical elements and electronics created simultaneously.
Advantages of wafer-level integration: close proximity of circuits and mechanical components reduces electromagnetic noise; potential for small package dimensions.
Disadvantages of monolithic integration:
1. Chip footprint mismatch: Micromechanical components may be larger, increasing die size.
2. Material complexity: Interwoven materials and processing can increase fabrication complexity and costs.
Chip-level integration involves separate micromechanical and circuit dies inserted into the same package and connected electrically with bonding wires.
It avoids material and processing coupling issues but increases distance between circuitry and mechanical elements.
Board-level integration connects micromechanical and circuit packages at the circuit board level with the longest wiring distance and the largest electronics noise.

2.5.2 Encapsulation

Encapsulation (sealing, vacuum packaging) places MEMS devices hermetically into a stable environment (e.g., vacuum, controlled pressure/humidity).
Commercially successful MEMS products are encapsulated in controlled or low-pressure environments.
Encapsulation can be performed at the wafer or package level.
Wafer-level encapsulation offers the greatest potential for miniaturization and automation.
Integration and packaging decisions should be made before design and process flow.

2.6 New Materials and Fabrication Processes

Silicon micromachining is augmented with new materials and processes.
Polymers, such as silicone elastomers, Parylene, and polyimide offer unique properties (biocompatibility, optical transparency), processing techniques, and low costs.
Sensors and actuators in harsh conditions require inorganic materials.
Silicon carbide (bulk and thin film) is used for high-temperature electronics and transducers.
Diamond thin films provide high electrical conductivity and wear resistance for pressure sensors and scanning electron microscopy probes.
Compound semiconductors, including GaAs are being investigated.
Other metal elements have also been involved in MEMS devices, including nickel, titanium, etc.
New processes include laser-assisted etching, stereo lithography, local electrochemical deposition, photo-electroforming, high aspect ratio deep reactive ion etching, micro milling, focused ion beam etching, X-ray etching, micro electro discharge, ink jet printing, micro contact printing, in-situ plasma, molding, embossing, screen printing, electrochemical welding, chemical mechanical polishing, micro glass blowing, and guided/self-directed self-assembly.

2.7 Process Selection and Design

Process design accommodates desired materials, enables high yield, and produces low-cost, high-performance devices.

2.7.1 Points of Consideration for Deposition Processes

Evaluate:
1. Ultimate thickness: Practical limits to film thickness.
2. Deposition rate and control factors: High speed vs. material quality.
3. Temperature of the process.
4. Deposition profile: Conformal, non-conformal, partial/complete planarization.

2.7.2 Points of Consideration for Etching Processes

Evaluate:
1. Etch rate: Speed of material removal.
2. End point detection: Determining when the process is finished.
3. Etch rate selectivity: Ratio between the etch rate of the targeted material and that of nonintended materials; ideally as large as possible.
4. Processing temperature: Temperatures of the bulk and the etching medium are highly relevant.
5. Etch uniformity across a wafer: Nonuniform etch rate complicates process control.
6. Sensitivity to overtime etch: Over-time etch is unavoidable.A robust process that is insensitive to over etch is always desirable.
7. Safety and cost of etchants: Material safety data sheet (MSDS) of a given product should always be consulted and strictly adhered to.
8. Surface finish and defects: Smoothness influences device and material performance.

2.7.3 Ideal Rules for Building a Process Flow

A MEMS process is based on layer-by-layer buildup of functional materials and selective etching.
Ideal Process Rule (IPR) #1: Any layer deposited on a wafer should not physically, thermally, or chemically damage or compromise layers already on the wafer.
Ideal Process Rule (IPR) #2: Any etching agent for removing one layer of material should ideally not attack other materials at all.

2.7.4 Rules for Building a Robust Process

A robust process achieves high yield with a broad range of tolerance for materials and process variability.
Uncertainties and inadequate etch rate selectivity can make a process nonrobust.
Uncertainties:
* Deposition rates and etch rates are variable
*Determining the endpoint of process is uncertain
* Material characteristics may be uncertain or variable
Process selectivity between target and masking materials should ideally be 5:1 or greater. A successful MEMS design musts navigate the available materials and processes to reach design specifications and price targets.
The best approach to deal with etching process uncertainties is to use process steps that are highly selective, so that they are virtually self-terminating when the endpoint has been reached, allowing moderate over-time process to mitigate process errors.