3_DAY_REPORT revised with Abbreviations(1)

Page 1: Lecture Schedule

  • Event: Advancements in Semiconductor Technologies

  • Dates: 18-12-2024 to 20-12-2024

  • Organizers: Naman Jain (Indian Institute of Information Technology Guwahati) and Krushna Dinesh Rane (Indian Institute of Technology Roorkee)

Schedule Breakdown

  1. 18th December 2024

    • Session: Development & Future Trends of 3D-IC Packaging Technology

    • Duration: 1.5 hours (11:30 AM - 1 PM), 1.5 hours (2:30 PM - 4 PM)

    • Speaker: Prof. Chang-Chun Lee, Department of Power Mechanical Engineering, NTHU

  2. 19th December 2024

    • Session: Manufacturing Processes of Advanced Nano Devices

    • Duration: 3 hours (9:30 AM - 12:30 PM), 3 hours (2 PM - 5 PM), 2 hours (11:30 AM - 1 PM)

    • Speaker: Prof. Tsung-Chieh Cheng, Department of Mechanical Engineering, National Kaohsiung University of Science and Technology

  3. 20th December 2024

    • Session 1: The Trends of Advanced Heterogeneous Integration Packaging

    • Duration: 3 hours (9:30 AM - 12:30 PM)

    • Speaker: Prof. Meng-Kai Shih, Department of Mechanical and Electromechanical Engineering, National Sun Yat-sen University, Kaohsiung

    • Session 2: The Development of Semiconductor Industry and Technology in Taiwan

    • Duration: 2 hours (3:30 PM - 5:30 PM)

    • Speaker: Dr. Yu-Hua Huang, Program Manager, TCSFT, NTHU

Highlights

  • Taiwan’s contributions to global semiconductor technology

  • Trends in semiconductor R&D and industrial growth

Page 2: Future Trends of 3D-IC Packaging Technology

Introduction

  • Concept of More Than Moore from a Taiwanese perspective, referring to innovations extending beyond traditional scaling of transistors as per Moore’s Law.

Course Outline

  • Fan-Out Packaging Development and Status

  • 3D IC Packaging Trends and Key Technologies

  • Heterogeneous IC Packaging Development

  • Scaling Trends Briefing:

    • Scaling semiconductor components from 90 nm down to 1 nm.

Basics of Wafer-Level Packaging (WLP)

  • WLP is an integral process in IC manufacturing, packaging done at the wafer level before dicing.

Types of WLP:

  1. Fan-in WLP:

    • Size matches die size with connections within the die area.

  2. Fan-out WLP:

    • Expands beyond chip area for additional component integration (SiP).

Technologies:

  • Fan-in: Redistribution Layer (RDL) and bumping (solder bumps).

  • Fan-out: Wafer reconstruction and integration of active devices.

Page 3: Comparison of Fan-out and Fan-in Packaging

Key Aspects:

  • Connection Distribution:

    • Fan-out: Spreads connections outward increasing pin density.

    • Fan-in: Limits connections within die area, affecting potential I/O.

  • Package Size:

    • Fan-out: Can reduce package size due to efficient connection distribution.

    • Fan-in: Generally larger due to limited density.

  • Application:

    • Fan-out is suited for high-performance devices needing many I/O connections.

    • Fan-in works for simpler designs with basic I/O requirements.

TSV and Microbump Technology in IC Packaging

  • TSV (Through Silicon Via): Vertical electrical pathways in 3D stacking configurations.

  • Microbumps: Connects stacked chips on TSVs enabling complex circuitry with lower footprint.

Page 4: CoWoS and InFO Technologies

CoWoS Technology:

  • Description: Chip-on-Wafer-on-Substrate, enabling integration of multiple chips in a package.

TSMC’s InFO Technology:

  • Description: Advanced packaging, RDL created directly on wafer with wider connections.

Types of InFO:

  1. InFO PoP: Stacks memory chips on processors (mobile devices).

  2. InFO oS: Larger packages for high-performance systems.

Points Concluded:

  • Importance of IC packaging in protecting from environmental factors and ensuring efficient power delivery.

Page 5: Advanced IC Packaging Techniques

Wafer-Level Packaging (WLP) and Chip-Scale Packaging (CSP)

  • WLP: Package at wafer level; CSP: Compact packages close to die size.

Panel-Level Packaging (PLP):

  • Uses rectangular panels, allowing for larger batch processing at lower cost.

Comparison of WLP and PLP:

Aspect

WLP

PLP

Chip Integration

Limited

Greater

Cost

Higher

Lower

Reliability Tests:

  • Thermal Cycle Test (TCT): Assess durability under temperature variations.

Page 6: Heterogeneous vs. Homogeneous Packaging

Definitions:

  • Homogeneous Packaging: Combines similar functionality chips (e.g., memory).

  • Heterogeneous Packaging: Integrates diverse functionalities (e.g., processors and GPUs).

Fan-In and Fan-Out Packaging:

  • Fan-In WLP: Contains interconnections limited to chip area.

  • Fan-Out WLP: Significant expansion using RDL, improving connection capacities.

Page 7: Day 2 Summary - Manufacturing Processes of Advanced Nano Devices

Overview:

  • Historical evolution of memory manufacturing processes and trends in the semiconductor industry.

Key Semiconductor Trends:

  1. Increased chip performance via smaller features.

  2. Enhanced reliability through design advancements.

  3. Reduced process costs through scaling.

Evolution of Wafer Size:

  • Timeline: From 50 mm in 1965 to 300 mm by 2000.

FinFETs Explained:

  • Significance: 3D structure minimizing short-channel effects and enhancing performance.

Pages 8-31: Further Elaborations on Semiconductor Manufacturing

FinFET vs. Planar MOSFET:

  • Decrease in leakage current, improved power efficiency, rapid switching speeds in FinFETs.

CVD and PVD Processes:

  • Thin film deposition methods with a focus on varying techniques.

Immersion Lithography’s Role:

  • Aids in achieving higher resolution through fluids.

Comparative Analyses of Various Technologies:

  • Highlights of wafer-level technologies, IC fabrication methods, and their unique advantages.

Integrated Circuit Technologies:

  • Discusses the evolution and application of various IC construction methodologies.

Advanced Packaging Comparisons:

  • EMIB vs. 2.5D interposers illustrating design and cost efficiency.

Hsinchu Science Park Overview:

  • Taiwan's semiconductor industry hub and its advantages.

Final Conclusions:

  • Comprehensive insights in semiconductor advancements, ongoing trends, and projected growth.

Used Abbreviations:

  • Key abbreviations relevant to semiconductor technology for quick reference.