A1 Computer Fundamentals Notes

Theme A: Concepts of computer science

  • A1 Computer fundamentals
    • Syllabus content hours (SL/HL): 11 / 18
  • A2 Networks
    • Syllabus content hours (SL/HL): 11 / 18
  • A3 Databases
    • Syllabus content hours (SL/HL): 11 / 18
  • A4 Machine learning
    • Syllabus content hours (SL/HL): 5 / 18
  • Theme B: Computational thinking and problem-solving
    • B1 Computational thinking
    • B2 Programming
    • B3 Object-oriented programming
    • B4 Abstract data types – HL only (not applicable for SL)
    • Case study: SL 15, HL 30
    • Internal assessment: SL 35, HL 35
    • The computational solution: SL 35, HL 35
    • Collaborative sciences project: SL 10, HL 10
  • Total teaching hours
    • SL 150, HL 240

A1.1 Computer hardware and operation

  • Describe the functions and interactions of the main CPU components
    • Key units: Arithmetic Logic Unit (ALU), Control Unit (CU)
    • Registers: Instruction Register (IR), Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), Accumulator (AC)
    • Buses: Address Bus, Data Bus, Control Bus
    • Processors: Single-core processor, Multi-core processor, Co-processors
    • Includes a diagrammatic representation of the relationship between these CPU components

The CPU and its common diagrams

  • Processor (CPU) schematic highlights
    • CU connected to ALU
    • Internal registers: IR, PC, MAR, MDR, AC
    • Buses link CPU with Primary Memory (RAM, ROM) via Address Bus and Data Bus
    • Typical depiction: CU → ALU, MAR/MDR as memory interfacing elements, with Input/Output paths
  • Diagram reference
    • Figure 2.2: CPU block diagram (CPU, CU, ALU, MAR, MDR, Input, Output, Memory Address Bus, Data Bus, Primary Memory RAM/ROM)
    • Source: Dimitrou K 2015, Core Computer Science, Express Publishers

The input–process–output model

  • A general model of computer operation
    • Input → Process → Output
    • Storage as needed between stages
  • Diagram reference
    • Figure 2.1: The input, process and output model
    • Source: Dimitriou K 2015, Core Computer Science, Express Publishers

Architecture of a CPU

  • The CPU is the hardware component that performs basic arithmetic, logic, and I/O operations
  • It processes data from input devices into useful information
  • Core elements
    • Hardware components: CPU, registers, buses
    • Central idea: fetch, decode, and execute instructions
  • Source: Dimitrou K 2015, Core Computer Science, Express Publishers

CPU components and their roles

  • Components inside the CPU
    • Control Unit (CU): Manages CPU operations, retrieves information from memory, and orders instruction execution
    • Fetch–decode–execute cycle: fetch instruction, decode it, execute the operation
    • Arithmetic Logic Unit (ALU): Performs arithmetic (e.g., addition, subtraction) and logical operations (e.g., AND, OR)
  • Registers (temporary storage within the CPU)
    • Purpose: very small, high-speed storage locations used to hold data temporarily during program execution
  • Summary: registers, buses, and core processing units work together to execute instructions efficiently

Detailed registers

  • Instruction Register (IR)
    • Holds the current instruction being executed
    • Acts as a temporary holding area before the instruction is decoded and carried out
  • Program Counter (PC)
    • Stores the address of the next instruction to be executed
    • Automatically increments after each instruction, always pointing to the next step in memory
  • Accumulator (AC)
    • Special-purpose register for storing intermediate results
    • Heavily used in arithmetic and logical operations
    • Can also act as temporary storage for other data types

Buses: CPU interconnects

  • A bus is a shared communication pathway that transfers data between components within a computer
  • Key buses connecting the CPU with other components
    • Control Bus
    • Carries control signals from the Control Unit to other components
    • Manages actions and timing of the CPU and memory
    • Signals can be unidirectional or bidirectional
    • Examples: Read/Write commands, interrupt signals, timing, acknowledgments
    • Data Bus
    • Transfers actual data between the CPU, memory, and other components
    • Bidirectional (data flows both to and from the CPU)
    • Bus width (e.g., 32-bit, 64-bit) affects how much data can move at once and influences speed
    • Address Bus
    • Carries memory addresses from the CPU to memory or I/O devices
    • Indicates where data should be read from or written to
    • Unidirectional (addresses flow out from the CPU)

Bus anatomy: at-a-glance comparison

  • Purpose alignment
    • Address Bus: tells CPU where to go in memory
    • Data Bus: carries the actual information
    • Control Bus: orchestrates actions and timing
  • Directionality
    • Address Bus: Unidirectional (CPU → memory)
    • Data Bus: Bidirectional
    • Control Bus: Generally Bidirectional (control signals sent/received)
  • Content Type
    • Address Bus: Memory location identifiers
    • Data Bus: Actual bytes, instructions, or data
    • Control Bus: Read/write control, acknowledgement, timing, interrupts
  • Width (Typical)
    • Address/Data: Varies by system, matching CPU word size
    • Control: Generally narrower (limited lines) because it carries signals, not large data
  • Role
    • Address Bus: Tells CPU where to go
    • Data Bus: Carries the data
    • Control Bus: Orchestrates actions and timing

Types of CPU processors

  • Single-core processors
    • One processing unit (one core) on a single chip
    • Executes one instruction at a time (sequential execution)
    • Was standard in early computers
    • Limitation: struggles with multitasking and parallel processing
  • Multi-core processors
    • Two or more cores on a single chip
    • Each core can process different instructions simultaneously
    • Improves performance for multitasking and parallel processing
    • Common in modern devices (e.g., dual-core, quad-core, more than 128 cores in servers)

Comparative parameters of CPU cores

  • Table (summary):
    • Single-Core: No. of cores = One primary core; Processing = Sequential; SMT = Not Possible; Power = Low; Speed = Slow; Efficiency = Low; Operation = One task at a time
    • Multi-Core: No. of cores = Two or more separate cores; Processing = Parallel; SMT = Possible; Power = High; Speed = Fast; Efficiency = High; Operation = Multitasking
  • Interpretation
    • Multicore enables parallelism and multitasking, at the cost of higher power consumption and capacity constraints within a single chip

Co-processors

  • Co-processors are specialized processors that support the main CPU
  • They offload specific tasks to improve efficiency
  • Common examples
    • Graphics Processing Unit (GPU): handles rendering images and video
    • Digital Signal Processor (DSP): handles signal and audio processing
  • Effect: frees the CPU to focus on general-purpose tasks while the co-processor accelerates specialized workloads

Key terms and concepts

  • Parallel Processing
    • Definition: Multiple processors/cores work simultaneously on parts of a task
    • Benefit: Increases speed and efficiency for suitable tasks
  • Architecture
    • Definition: The design and structure of computer hardware and software
    • Impact: Determines how tasks are performed and how efficiently they are executed
  • Rendering
    • Definition: Generating an image from model data by performing computational tasks
    • Example: Turning 3D scene data into a 2D image ready for display

Visual references referenced in the notes

  • Figure 2.2: CPU block diagram
    • Shows the relationship among CU, ALU, IR, PC, MAR, MDR, input/output, and memory buses
    • Source: Dimitrou K 2015, Core Computer Science, Express Publishers
  • Figure 2.1: The input, process and output model
    • Emphasizes the flow: Input → Process → Output with storage as needed
    • Source: Dimitriou K 2015, Core Computer Science, Express Publishers

Connections to broader concepts

  • Foundational role of the CPU in computer systems: core engine for executing instructions that control software and hardware
  • Interaction with memory: MAR/MDR facilitate address/data flow between CPU and RAM/ROM via Address/Data Buses
  • Importance of buses: define how different components communicate; speed is influenced by bus width and directionality
  • Evolution of CPUs: from single-core to multi-core and inclusion of co-processors aligns with demands for multitasking, graphics, and real-time signal processing

Practical implications and considerations

  • Performance depends on core count, clock speed, bus width, and efficiency of the fetch–decode–execute cycle
  • Energy usage and thermal design are important for multicore systems and co-processors
  • Software design implications: parallelizable tasks can leverage multicore architectures; some tasks benefit more from GPUs or DSPs
  • Ethical and real-world relevance: efficient CPU design impacts energy consumption, device cost, performance of critical systems (e.g., healthcare, autonomous systems, data centers)