Operating Systems: Computer System Overview

Operating Systems: Definition and Basic Functions\n\n* Definition and Core Role: An Operating System (OS) is software that supports a computer's basic functions. This includes the scheduling of tasks, execution of applications, and control of peripherals.\n* Resource Management: The OS exploits the hardware resources of one or more processors to provide a set of services to system users. It is responsible for managing secondary memory and Input/Output (I/O) devices.\n* Academic Context: These principles are based on \"Operating Systems, Internal \u0026 Design Principles\" by Stallings, as presented at Fatima Jinnah Women University.\n\n# Computer System: Basic Elements and Internal Communication\n\n* Primary Hardware Elements: A computer consists of four main components:\n * Processor (CPU): Controls the operation of the computer and performs data processing functions.\n * Main Memory: Often referred to as real memory or primary memory. It is volatile, meaning data is typically lost when power is removed. It consists of a set of locations defined by sequentially numbered addresses and stores both data and instructions.\n * I/O Modules: These modules move data between the computer and the external environment, including storage (e.g., hard drives), communications equipment, and terminals.\n * System Bus: The communication mechanism providing connectivity among processors, main memory, and I/O modules.\n* Internal Processor Registers: Specialized storage locations within the processor:\n * Memory Address Register (MAR): Specifies the address in memory for the next read or write.\n * Memory Buffer Register (MBR): Contains the data to be written into memory or receives the data read from memory.\n * I/O Address Register (I/O AR): Specifies a particular I/O device.\n * I/O Buffer Register (I/O BR): Facilitates the exchange of data between an I/O module and the processor.\n\n# Top-Level View of Computer Components\n\n* The Processor Internal Structure: Contains the Program Counter ($PC$), Instruction Register ($IR$), and buffers ($MAR$, $MBR$, $I/O AR$, $I/O BR$), alongside an Execution Unit.\n* Main Memory Structure: Organized as a series of locations from $0, 1, 2, \dots, n-2, n-1$, containing instructions and data.\n* Interaction: The System Bus links these components, allowing the processor to fetch instructions from memory and exchange data with I/O modules via dedicated buffers and address registers.\n\n# Detailed Categorization of Processor Registers\n\n* Register Characteristics: Registers are faster and smaller than main memory.\n* User-Visible Registers: These enable programmers to minimize main memory references by optimizing register usage. They are available to all programs (application and system programs).\n * Data Registers: Often general-purpose, though some may be dedicated to specific tasks like floating-point or integer operations.\n * Address Registers: Include Index Registers (e.g., used in operations like $\text{MOV AX, [SI+300]}$ where $\text{SI}$ is the index register holding an offset), Segment Pointers, and Stack Pointers.\n* Control and Status Registers: Used by the processor to control operations and by privileged OS routines to control program execution.\n * Program Counter (PC): Contains the address of the instruction to be fetched.\n * Instruction Register (IR): Contains the most recently fetched instruction.\n * Program Status Word (PSW): Contains status information.\n * Condition Codes (Flags): Bits set by hardware as a result of operations (e.g., arithmetic results). These are read-only and provide feedback regarding instruction execution.\n\n# Instruction Execution and the Basic Instruction Cycle\n\n* Program Composition: A program is a set of instructions stored in memory.\n* The Two-Step Cycle:\n 1. Fetch Stage: The processor reads (fetches) instructions from memory. The $PC$ holds the address of the next instruction and is incremented after each fetch.\n 2. Execute Stage: The processor executes the fetched instruction loaded in the $IR$.\n* Instruction Categories: Fetched instructions typically fall into processor-memory, processor-I/O, data processing, or control categories.\n\n# Characteristics of a Hypothetical Machine\n\n* Instruction Format: A $16$-bit structure where bits $0-3$ represent the Opcode and bits $4-15$ represent the Address.\n* Integer Format: A $16$-bit structure with bit $0$ as the sign and bits $1-15$ as the magnitude.\n* Internal CPU Registers: Includes the Program Counter ($PC$), Instruction Register ($IR$), and the Accumulator ($AC$) for temporary storage.\n* Sample Opcodes:\n * $0001$: Load $AC$ from memory.\n * $0010$: Store $AC$ to memory.\n * $0101$: Add to $AC$ from memory.\n* Example Execution Trace:\n * Step 1: Fetch instruction at address $300$ ($1940$) into $IR$; $PC$ becomes $301$.\n * Step 2: Execute $1940$ (Load $AC$ from address $940$). $AC$ now contains the value at $940$ (e.g., $0003$).\n * Step 3: Fetch instruction at address $301$ ($5941$) into $IR$; $PC$ becomes $302$.\n * Step 4: Execute $5941$ (Add value at address $941$ to $AC$). If $941$ contains $0002$, $AC$ becomes $0005$.\n * Step 5: Fetch instruction at address $302$ ($2941$) into $IR$; $PC$ becomes $303$.\n * Step 6: Execute $2941$ (Store contents of $AC$ to address $941$). Memory at $941$ is updated to $0005$.\n\n# Interrupts: Enhancing Processor Utilization\n\n* Purpose: Interrupts improve processor utilization by allowing the processor to perform other tasks while waiting for slower I/O devices.\n* Classes of Interrupts:\n * Program: Result of instruction execution, such as arithmetic overflow, division by zero, illegal machine instructions, or memory access violations.\n * Timer: Generated by a processor timer, allowing the OS to perform regular functions.\n * I/O: Generated by I/O controllers to signal normal completion or error conditions.\n * Hardware Failure: Result of power failure or memory parity errors.\n\n# Interrupt Processing and Flow of Control\n\n* Flow of Control: In a system with no interrupts, the processor must wait for I/O commands to finish (e.g., a WRITE operation) before continuing common user program tasks. With interrupts, the processor can execute other instructions while I/O is pending.\n* Transfer of Control: When an interrupt occurs, the processor suspends the user program at instruction $i$, executes an Interrupt Handler, and then resumes at instruction $i+1$.\n* Instruction Cycle with Interrupts: The cycle includes an \"Interrupt Stage\" after the Execute Stage. The processor checks for pending interrupts; if enabled and present, it initiates the interrupt handler.\n* Hardware/Software Processing Steps:\n 1. Device controller issues interrupt.\n 2. Processor finishes the current instruction.\n 3. Processor signals acknowledgment.\n 4. Processor pushes $PSW$ and $PC$ onto the control stack.\n 5. Processor loads a new $PC$ value for the interrupt.\n 6. (Software) Save remaining process state.\n 7. (Software) Process the interrupt.\n 8. (Software) Restore process state.\n 9. Restore old $PSW$ and $PC$.\n\n# Multiple and Nested Interrupt Handling\n\n* Sequential Processing: Interrupts are disabled while an interrupt is being handled. Subsequent interrupts wait until the current handler finishes.\n* Nested (Priority) Processing: Allows a high-priority interrupt to interrupt a lower-priority interrupt handler. Control returns to the lower-priority handler once the high-priority task is finished.\n\n# The Memory Hierarchy\n\n* Constraints: Memory involves trade-offs between Capacity, Speed (Access Time), and Cost.\n * Faster access time = Greater cost per bit.\n * Greater capacity = Smaller cost per bit.\n * Greater capacity = Slower access speed.\n* Hierarchy Trends (Top to Bottom):\n * Decreasing cost per bit.\n * Increasing capacity.\n * Increasing access time.\n * Decreasing frequency of access by the processor.\n* Secondary Memory: Also known as auxiliary or external memory; it is nonvolatile and used for storing program and data files.\n\n# Cache Memory: Principles and Design\n\n* Purpose: Cache acts as a small, fast memory sitting between the processor and main memory. It is invisible to the OS and exploits the Principle of Locality.\n* Principle of Locality: Data required soon is often close to current data. If a data item is referenced, its neighbor is likely to be needed soon.\n* Operation: The processor checks the cache first. If the data is not found (a miss), a \"block\" of memory is read into the cache. Transfers between CPU and Cache happen in Words/Bytes, while transfers between Cache and Main Memory happen in Blocks.\n* Design Issues:\n * Cache Size: Even small caches significantly impact performance.\n * Block Size: The unit of data transfer. Larger blocks increase hits but too large a size reduces the chance of reuse.\n * Mapping Function: Determines which cache location a memory block will occupy.\n * Replacement Algorithm: Chooses which block to replace when a new one is loaded. The Least Recently Used (LRU) algorithm is an effective strategy.\n * Write Policy: Dictates when memory writes occur—either every time a block is updated or only when a block is replaced (to minimize operations).\n\n# I/O Communication Techniques\n\n* Programmed I/O: The processor executes an I/O instruction by issuing a command. It remains in a status-checking loop (busy-waiting) until the operation completes, reading data one word at a time.\n* Interrupt-driven I/O: Eliminates needless waiting. The processor issues a read command and then \"does something else.\" The I/O module interrupts the CPU when it is ready. The CPU then checks the status and writes the word into memory.\n* Direct Memory Access (DMA): Used for large volumes of data. The processor delegates the I/O operation to a separate DMA module. The processor provides command details (Read/Write, device address, starting memory location, and number of words) and is only involved at the beginning and end of the transfer. This is the most efficient technique as the DMA module handles the data exchange directly with memory.", "title": "Operating Systems: Computer System Overview"}