CLD-Lec6-Adders
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KOREA UNIVERSITY JF Core System
Components:
Agent & Processor
Memory Controller
Graphics including Display
DML and miscellaneous I/O
Course Information:
COSE221 Logic Design Lecture 6
Instructor: Dr. Ngoc-Son Pham, Computer Science & Engineering, Korea University
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Introduction
Topics Covered:
Basic skills in designing combinational and sequential logic using schematic and Verilog-HDL
Upcoming Focus Areas:
Arithmetic circuits: Adders and Subtractors
Counters
Shift Registers
Representation of floating-point numbers in C:
floatanddoubleMemory and Logic Arrays
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Arithmetic Circuits
Functions of Computers: Perform arithmetic operations
Addition, subtraction, comparison, shift, multiplication, division
Core focus:
Study of hardware implementations for these operations
Emphasis on Addition:
Most common operation in computers
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1-bit Half Adder
Implementation of a 1-bit adder:
Components:
2 inputs: A and B
2 outputs: S (Sum) and Cout (Carry)
Truth Table:
A
B
S (Sum)
C (Carry)
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
Logical Operations:
S = A XOR B
Cout = A AND B
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1-bit Full Adder
Enhancement of Half Adder:
Full adder has an additional input: Cin
Components:
3 inputs: A, B, Cin
2 outputs: S, Cout
Truth Table:
Cin
A
B
S (Sum)
Cout
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
Logical Operations:
S = A XOR B XOR Cin
Cout = A AND B + Cin(A XOR B)
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1-bit Full Adder Detailed
Diagram Representation:
Inputs: A, B, Cin
Outputs: Sum (S), Carry out (Cout)
Relations:
S = A XOR B XOR Cin
Cout = AB + (Cin(A XOR B))
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1-bit Full Adder Schematic
Block diagram implementation:
Involves two half adders and an OR gate
Connectivity:
Cout is derived from the Carry of Half Adders' outputs
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Multi-bit Adder
Concept of extending 1-bit adders to N-bit adders
Definitions:
N-bit adder sums two N-bit inputs along with carry-in (Cin)
Types of implementations for Carry Propagate Adders (CPAs):
Ripple-carry adders (Slow)
Carry-lookahead adders (Fast)
Prefix adders (Faster)
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Ripple-Carry Adder
Method of chaining 1-bit adders
Carry ripples through the entire chain
Example:
32-bit Ripple Carry Adder diagram
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4-bit Ripple-Carry Adder Full Adder Chain
Configuration:
Series of full adders designed to sum 4 bits each
Carry from previous adder to next
Relationships:
S0: Sum[0], S1: Sum[1], etc.
Cout derived as described earlier
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Delay of Ripple Carry Adder
Critical Path Analysis:
1st Stage critical path = 3 gate delays
Considerations:
Types of gates: XOR, AND, OR
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Delay Timing Analysis of Ripple Carry Adder
2nd Stage Critical Path = 2 gate delays
Implications for performance:
Ripple carry causes delays in large bit-size adders
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Ripple-Carry Adder Critical Path Delay
Critical path for 4-bit adder = 9 gate delays
General formula for N-bit adder:
2(N-1)+3 = (2N+1) gate delay
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Ripple-Carry Adder Disadvantages
Discussed performance issues:
Slow operation for large N (triples delay)
Need for alternative faster designs
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Carry-Lookahead Adder (CLA)
Purpose: Overcome slow propagation in ripple carry adders
Mechanism:
Divides the adder into functional blocks
Generates carry-outs quickly using additional circuitry
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Carry Calculation in CLA
For N-bit block, the carry-out (Cout) is computed based on generating and propagating signals
Relationships:
Gi = Ai AND Bi
Pi = Ai OR Bi
Carry Generation: Ci = Gi + Pi Ci-1
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Carry Generation & Propagation
Description of the propagation of carries through different bits
Computation of final carry-out from chained generate/propagate signals
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4-bit CLA Block
Understanding the operation of a 4-bit block in CLA
Building up carry-out from the generate/propagate calculations
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CLA Logic Implementation
Overview of CLA components:
Integrating carry lookahead logic with other operations
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CLA Implementation Detail
Description of a CLA circuit with logic gates
Time complexity reduced due to fewer gate delays compared to ripple carry
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32-bit CLA with 4-bit Blocks
Diagrammatic representation of a CLA design
Structure exemplifies block-wise addition leading to speed enhancement
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CLA Delay Analysis
Formula for estimating delay in CLA circuits based on various gates' properties
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Adder Delay Comparisons
Comparative delay analysis for ripple-carry vs. CLA
Example delays based on assumed gate timing
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Verilog-HDL Representation
Example code defining an adder in Verilog-HDL:
module adder #(parameter N = 8) (input [N-1:0] a, b, input cin, output [N-1:0] s, output cout);
assign {cout, s} = a + b + cin;
endmodulePage 25
When to Use What?
Overview of different types of adders:
Ripple-carry adder
Carry-lookahead adder
Prefix adder
Trade-offs:
Speed vs. Hardware complexity and cost
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Backup Slides
Additional, detail-oriented slides
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Implementation of Carry Lookahead Logic
Detailed example of CLA
Explanation of carry delay calculations based on gate propagation
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Prefix Adder
Mechanism of calculating generate and propagate signals
Descriptive walkthrough of how the prefix structure operates
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Prefix Adder Continuing Theory
Further detailing of carry calculations for prefix adder
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Prefix Adder Signal Computation
Generation and propagation signals for addition
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4-bit Prefix Adder
Design example showcasing add operation using prefix logic
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16-bit Prefix Adder Structure
Breakdown of prefix adder with detailed connections and relationships between signals
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Prefix Adder Delay Analysis
Final calculations for prefix adder delay based on architectural layout and gate delays