COA-4th chapter

Definition: A structured organization of different memory types in layers based on speed, size, and cost.
Purpose: Optimizes performance by balancing access speed with cost and storage capacity.

Registers (Level 1)
- Speed: Fastest
- Size: Small (in bytes)
- Cost: Expensive
- Function: Store data and instructions for immediate processing.
Cache Memory (Level 2)
- Speed: Very fast (slower than registers, faster than main memory)
- Size: Small (1-16MB)
- Cost: Expensive
- Function: Stores frequently accessed data to reduce access time from slower memory levels; divided into L1, L2, L3.
Main Memory (Level 3)
- Speed: Slower than cache memory
- Size: Larger (4GB-64GB)
- Cost: Moderate
- Function: Holds active data and programs being used.
Secondary Memory (Level 4)
- Speed: Slower than RAM
- Size: Very large (hundreds of GB to multiple TB)
- Cost: Relatively cheap
- Function: Stores data persistently, even when powered off.

Fast Data Access: Reduces time to retrieve data by storing frequently accessed items in faster memory.
Reduced Latency: Ascends performance by moving data closer to the CPU.
Cost-Effectiveness: Balances performance and affordability through a tiered system.
Efficient Memory Usage: Storing more frequently used data in the cache.

Speed vs. Size: Fast memory types (registers, cache) are smaller in capacity than slower types (RAM, disk).
Cost vs. Performance: Faster memory (cache) is more expensive than slower memory (HDD, DRAM).
Complexity vs. Efficiency: Multiple levels introduce complexity in managing data and require algorithms for data replacement in caches.
Energy Consumption: Fast memory consumes more energy; accessing data from registers and caches requires more power than secondary storage.

Definition: Acts as a buffer between the main memory and CPU.
Purpose: Stores frequently accessed data to reduce access time from the slower main memory.

CPU Request: CPU requests data from the main memory.
Cache Check: The cache controller checks if the data is stored.
Cache Hit: If found, data is retrieved from the cache.
Cache Miss: If not found, data is fetched from main memory and stored in cache.
Data Retrieval: CPU retrieves data from the cache.

Associative Mapping: Flexible, stores both address and data; avoids index collision.
Direct Mapping: Simpler, divides memory address into index and tag fields; can lead to collisions.
Set-Associative Mapping: Combines features of both mappings, allowing multiple addresses to map to the same index.

Programmed I/O: Data transfers initiated by instructions in the program, requiring CPU to monitor interfaces.
- Advantage: Simplicity in implementation.
- Disadvantage: CPU wait times can degrade performance.
Interrupt-Driven I/O: Device generates an interrupt request when ready for data transfer.
- Advantage: CPU doesn't wait and can perform other tasks.
- Disadvantage: Overhead of handling interrupts.
Direct Memory Access (DMA): Allows devices to transfer data to memory directly without CPU intervention.
- Advantage: Frees up CPU for other tasks, enhances transfer speed.
- Disadvantage: More complex hardware requirements.

Asynchronous Data Transfer: Data transfers occur without synchronized clock signals; uses start/stop bits for signaling.
- Advantages: Flexibility in transfer timing.
- Disadvantages: Slower transfer speeds compared to synchronous transfers.
Synchronous Data Transfer: Data sent in a continuous stream synchronized by clock signals.
- Advantages: Higher data transfer rates, precise timing.
- Disadvantages: Complexity in maintaining clock synchronization.