Transistor Fabrication and FinFET Process Overview

Transistor Fabrication Overview

Key Components of Transistors

  • Transistor Structure: The essential components of a transistor include:

    • Source Area

    • Drain Area

    • Gate Area

  • The order of fabrication of these components is critical to the overall performance of the transistor.

Historical Context

  • Early Transistor Fabrication: Initially, a planar transistor was fabricated with the following characteristics:

    • Gate Material: Initially used polysilicon due to its simple process.

    • Threshold Voltage: Symmetrical threshold voltages between n and p transistors were easier to achieve.

  • Disadvantages of Polysilicon Gates:

    • High Access Resistance: Polysilicon possesses higher resistance than metals, causing slower transistor speeds due to increased time constants ($ au = R imes C$).

    • Accumulation of Charge: Charge accumulation could create a depletion region, leading to voltage drops.

    • Anisotropic Etching Issues: Anisotropic etching could lead to damage in areas around the gate, increasing gate current and losses.

Transition to Metal Gates

  • Replacement of Polysilicon with Metal: The introduction of the replace metal gate process improved transistor performance:

    • Advantages of Metal Gates:

    • Lower resistance than polysilicon leading to improved speed and efficiency.

    • Resolution of issues related to charge accumulation and depletion regions.

  • Order of Fabrication Steps: In the new methodology due to metal gates:

    1. Creation of a Dummy Gate: Amorphous silicon is typical; this gate does not function but acts as a protective shield.

    2. Source and Drain Fabrication: These are defined with respect to the dummy gate.

    3. Removal of Dummy Gate and Metal Gate Fabrication.

  • Historical Overview of Gate Usage:

    • Early transistors utilized polysilicon gates, while modern designs favor metal gates for better electrical performance.

Fabrication Process Steps

  • Initial Layer: Start with a substrate covered with multiple fins, which are crucial for the FinFET design.

1. Dummy Gate Creation

  • Masking Process: Masking is crucial to cover certain areas while exposing the desired gate area.

  • Thermal Oxidation Step:

    • A thin layer of silicon dioxide (approximately 1 nm) is produced via thermal oxidation from the silicon fins. This oxidation serves as an etch stop layer for future processes and protects the fins during further fabrication.

    • Effects of Thermal Oxidation: It reduces the fin's thickness, facilitating scaling in transistor size.

2. Creating the Source and Drain Areas

  • These are like the entry and exit points for electricity in your transistor. The Source is where the current typically starts, and the Drain is where it exits.

  • This step happens after we've put in the temporary "dummy gate" (which acts as a placeholder) but before we put in the final, working metal gate. The dummy gate is there to protect the channel region during the intense processes used to create the Source and Drain.

  • LDD Extensions (Lightly Doped Drain Extensions):

    • Think of these as special, slightly less "doped" (meaning they have fewer impurities added to change their electrical properties) regions that extend from the main Source and Drain areas towards the gate.

    • Why are they needed? When we create the "spacers" (which we'll talk about next), they can sometimes make it harder for current to flow smoothly right next to the gate. This resistance is called "access resistance." LDD extensions help to smooth this transition and reduce this resistance, ensuring the transistor works efficiently. They also help to reduce strong electric fields near the gate, which can damage the device over time.

  • Spacers:

    • These are insulating walls made of silicon nitride that are built on the sides of the gate.

    • Their main job is electrical insulation. They prevent electrical short circuits between the gate (which controls the transistor) and the Source/Drain regions (where the current flows), ensuring that the gate signal only influences the channel underneath it, not the surrounding areas.

3. Doping Procedure

  • Preceding doping, a thin protective layer of silicon carbon nitride is applied over the fins.

    • Ion Implantation Technique: It is essential to angle the doping (e.g., 10 degrees) to avoid concentration at the top due to the high aspect ratio of the fins. This technique allows more effective placement of dopants throughout the structure of the fin.

      • Thermal Annealing: After we implant the dopants (the impurities that change electrical properties), we perform a thermal annealing process. This is like putting the whole thing in a special oven; it's done to wake up the dopants and fix any damage caused by the implantation. - What it does: Think of the silicon fin as a perfectly arranged LEGO structure. When we shoot ions (dopants) into it during implantation, some LEGO bricks (silicon atoms) get knocked out of place, and the new dopant LEGOs just land wherever they can. - Activating Dopants: The annealing step heats everything up just enough so that the implanted dopant atoms can wiggle and settle into the correct, organized spots within the silicon crystal structure. Once they are in these correct spots, they can actually start doing their job of conducting electricity. If they stay in the wrong spots, they don't help much with the electrical flow, and the transistor won't work right.- Fixing Damage (Mitigating Damage): The high-speed dopant ions can also accidentally smash into and dislodge some of the silicon atoms, creating tiny broken spots or

4. Creation of Spacers

  • After doping is successfully accomplished with appropriately angled ions, the next step involves:

    • Depositing Silicon Nitride: An insulating layer is applied. This material protects against contamination and damage.

    • Planarization and Anisotropic Etching: After planarizing the silicon nitride layer, anisotropic etching is conducted to form the final spacer structure, thereby preparing the fin for the next stages of fabrication.

Final Steps for Transistor Completion

  • Completion of Source and Drain Areas: Should be integrated with the fabrication of the metal gate, which can occur only once the dummy gate is removed.

  • Understanding these processes and overcoming issues related to access resistance is crucial for achieving optimal performance in a FinFET transistor.

Conclusion

In summary, the construction of a FinFET requires precision in fabricating the dummy gate, source and drain areas, and eventually transitioning to a functional metal gate. The changes in material from polysilicon to metal significantly enhance the function and performance of modern transistors, driving advances in semiconductor technology.

Spacer Creation Outline
What are Spacers?

  • Insulating walls (silicon nitride)

  • Located on sides of dummy gate

  • Main Job: Electrical insulation

When are Spacers Created?

  • After dummy gate is in place

  • After Source/Drain areas (with LDD extensions) are defined and doped

  • Before dummy gate removal and final metal gate fabrication

Key Steps to Create Spacers:

  1. Depositing Silicon Nitride layer

  2. Planarization of the layer

  3. Anisotropic Etching to shape walls