Computer Organization and Architecture Notes

Computer Architecture versus Computer Organization

Computer architecture deals with the functional specifications and operational attributes of a computer system as viewed by a programmer. It encompasses the Instruction Set Architecture (ISA), memory addressing techniques, data representation bit widths, and input-output mechanisms. It fundamentally defines what a computer system does from an abstract perspective.

In contrast, computer organization describes the physical realization and microarchitectural implementation of the specifications set by the architecture. It focuses on how individual hardware components, control signals, adders, circuit designs, and peripheral interfaces are physically interconnected and coordinated to fulfill operational requirements.

Computer Generations

Computer history is categorized into five distinct generations based on advancements in core hardware components and software structures. First-generation computers (1946–1959) utilized vacuum tubes for CPU logic and memory circuitry, supported machine language, and relied on batch processing systems such as ENIAC, EDVAC, and UNIVAC.

Second-generation computers (1959–1965) substituted vacuum tubes with transistors, introducing magnetic core main memory alongside high-level programming languages like FORTRAN and COBOL. Third-generation computers (1965–1971) adopted Integrated Circuits (ICs), developed by Jack Kilby, which enabled time-sharing operating systems, increased reliability, and smaller physical footprints.

Fourth-generation computers (1971–1980) incorporated Very Large Scale Integrated (VLSI) circuits containing thousands of transistors on a single chip, ushering in the personal computer revolution and distributed networking. Fifth-generation computers (1980–present) leverage Ultra Large Scale Integration (ULSI) technology alongside parallel processing hardware and artificial intelligence software applications.

Functional Units and Operational Concepts

A digital computer consists of five primary functional units: Input, Memory, Arithmetic Logic Unit (ALU), Output, and Control Unit. Input devices convert user information into binary code, while output units return processed results. The ALU executes arithmetic and logical micro-operations on operands fetched from memory into internal processor registers. The memory unit stores active instructions and data in primary semiconductor storage, alongside secondary storage media for long-term data retention. The control unit coordinates all operations by issuing precise timing and control signals.

In the Von Neumann computer model, instructions and data are stored in a single unified main memory. Program execution begins by setting the Program Counter (PC) to the address of the first instruction. This address transfers to the Memory Address Register (MAR), a read control signal fetches the instruction into the Memory Data Register (MDR), and it is moved into the Instruction Register (IR) for decoding and execution. Standard program execution can be preempted by hardware interrupts, prompting the processor to store its active state in memory and execute an interrupt service routine before resuming the original process.

Bus Structures and Processor Performance

A bus is a collection of signal lines used to transfer data, address, and control information between system components. A single-bus structure links all primary functional units over one shared pathway, providing a low-cost structure at the risk of communication bottlenecks. A multiple-bus structure utilizes separate interconnected pathways to enable parallel data transfers and higher overall throughput.

System performance depends on processor execution time $T$, defined by the basic performance equation:

$T = \frac{N \times S}{R}$

Here, $N$ represents the total instruction count, $S$ represents the average clock cycles per instruction, and $R$ represents the clock rate in cycles per second. Performance can be maximized by overlapping instruction cycles through pipelining or implementing superscalar execution with multiple parallel instruction pipelines.

Instruction Set Architecture and Addressing Modes

Instruction set architectures are broadly categorized as Complex Instruction Set Computers (CISC) or Reduced Instruction Set Computers (RISC). CISC designs feature extensive instruction sets, variable instruction lengths, multiple addressing modes, and microprogrammed control logic. RISC designs emphasize simple, fixed-length instructions executed in a single clock cycle, hardwired control units, large register files, and memory access strictly limited to explicit load and store instructions.

Addressing modes define how operands or effective addresses are calculated during instruction execution. Primary modes include immediate addressing where the operand is contained within the instruction, direct addressing referencing a memory location, indirect addressing referencing a pointer location in memory, register addressing specifying a register containing the operand, and register indirect addressing referencing a register holding a memory address. Displacement modes combine base registers or program counters with relative offsets, enabling base-register addressing, relative addressing, and auto-indexing.

Control Units and Memory Hierarchy

Control units generate micro-operation sequences using either hardwired or microprogrammed implementations. Hardwired control units utilize fixed combinational logic and sequential state machines to yield high execution speed. Microprogrammed control units store control words as microinstructions inside a dedicated Control Memory (ROM or RAM). The Control Address Register (CAR) specifies the next microinstruction location, which is loaded into the Control Data Register (CDR) to trigger control signals.

Memory systems employ a hierarchical structure balancing access speed, storage capacity, and cost per bit. Fast internal registers and static RAM (SRAM) cache memories buffer frequently accessed instructions near the processor. Main memory consists of dynamic RAM (DRAM), which requires periodic refresh cycles due to charge dissipation on storage capacitors. Virtual memory managed by a Memory Management Unit (MMU) maps logical virtual address spaces onto physical main memory and secondary storage.

Direct Memory Access (DMA) controllers enable high-speed data transfers directly between peripheral I/O devices and main memory without routing data through the central processor. Redundant Array of Independent Disks (RAID) configurations organize multiple secondary disk drives into arrays using striping, mirroring, or parity checking to achieve enhanced data reliability, fault tolerance, and high I/O throughput.

Computer Architecture versus Computer Organization

Computer architecture deals with the functional specifications and operational attributes of a computer system as viewed by a programmer. It encompasses the Instruction Set Architecture (ISA), memory addressing techniques, data representation bit widths, and input-output mechanisms. It fundamentally defines what a computer system does from an abstract perspective.

In contrast, computer organization describes the physical realization and microarchitectural implementation of the specifications set by the architecture. It focuses on how individual hardware components, control signals, adders, circuit designs, and peripheral interfaces are physically interconnected and coordinated to fulfill operational requirements.

Computer Generations

Computer history is categorized into five distinct generations based on advancements in core hardware components and software structures:

• First-generation (1946–1959): Utilized vacuum tubes for CPU logic and memory circuitry, supported machine language, and relied on batch processing systems such as ENIAC, EDVAC, and UNIVAC.

• Second-generation (1959–1965): Substituted vacuum tubes with transistors, introducing magnetic core main memory alongside high-level programming languages like FORTRAN and COBOL.

• Third-generation (1965–1971): Adopted Integrated Circuits (ICs), developed by Jack Kilby, which enabled time-sharing operating systems, increased reliability, and smaller physical footprints.

• Fourth-generation (1971–1980): Incorporated Very Large Scale Integrated (VLSI) circuits containing thousands of transistors on a single chip, ushering in the personal computer revolution and distributed networking.

• Fifth-generation (1980–present): Leverages Ultra Large Scale Integration (ULSI) technology alongside parallel processing hardware and artificial intelligence software applications.

Functional Units and Operational Concepts

A digital computer consists of five primary functional units:

• Input: Converts user information into binary code.

• Memory: Stores active instructions and data in primary semiconductor storage, alongside secondary storage media for long-term retention.

• Arithmetic Logic Unit (ALU): Executes arithmetic and logical micro-operations on operands fetched from memory into internal processor registers.

• Output: Returns processed results to the user.

• Control Unit: Coordinates all operations by issuing precise timing and control signals.

In the Von Neumann computer model, instructions and data are stored in a single unified main memory. Program execution follows these sequential steps:

1. The Program Counter (PC) is set to the address of the first instruction.

2. This address transfers to the Memory Address Register (MAR).

3. A read control signal fetches the instruction into the Memory Data Register (MDR).

4. The instruction moves into the Instruction Register (IR) for decoding and execution.

Standard program execution can be preempted by hardware interrupts, prompting the processor to store its active state in memory and execute an Interrupt Service Routine (ISR) before resuming the original process.

Bus Structures and Processor Performance

A bus is a collection of signal lines used to transfer data, address, and control information between system components:

• Single-bus structure: Links all primary functional units over one shared pathway, providing a low-cost structure at the risk of communication bottlenecks.

• Multiple-bus structure: Utilizes separate interconnected pathways to enable parallel data transfers and higher overall throughput.

System performance depends on processor execution time $T$, defined by the basic performance equation:

$T = \frac{N \times S}{R}$

Where:

• $N$ = total instruction count

• $S$ = average clock cycles per instruction

• $R$ = clock rate in cycles per second

Performance can be maximized by overlapping instruction cycles through pipelining or implementing superscalar execution with multiple parallel instruction pipelines.

Instruction Set Architecture and Addressing Modes

Instruction set architectures are broadly categorized into two paradigms:

• CISC (Complex Instruction Set Computers): Feature extensive instruction sets, variable instruction lengths, multiple addressing modes, and microprogrammed control logic.

• RISC (Reduced Instruction Set Computers): Emphasize simple, fixed-length instructions executed in a single clock cycle, hardwired control units, large register files, and memory access strictly limited to explicit load and store instructions.

Addressing modes define how operands or effective addresses are calculated:

• Immediate Addressing: The operand is contained directly within the instruction.

• Direct Addressing: References a specific main memory location.

• Indirect Addressing: References a pointer location in memory.

• Register Addressing: Specifies a register containing the operand.

• Register Indirect Addressing: References a register holding a memory address.

• Displacement Modes: Combine base registers or program counters with relative offsets, enabling base-register addressing, relative addressing, and auto-indexing.

Control Units and Memory Hierarchy

Control units generate micro-operation sequences using two primary techniques:

• Hardwired Control: Utilizes fixed combinational logic and sequential state machines to yield maximum execution speed.

• Microprogrammed Control: Stores control words as microinstructions inside a dedicated Control Memory (ROM or RAM). The Control Address Register (CAR) specifies the next microinstruction location, which is loaded into the Control Data Register (CDR) to trigger control signals.

Memory systems employ a hierarchical structure balancing speed, capacity, and cost:

• Registers & Static RAM (SRAM) Cache: Fast internal memory buffering frequently accessed instructions near the processor.

• Main Memory (DRAM): Requires periodic refresh cycles due to charge dissipation on storage capacitors.

• Virtual Memory: Managed by a Memory Management Unit (MMU) to map logical virtual address spaces onto physical main memory and secondary storage.

• Direct Memory Access (DMA): Enables high-speed data transfers directly between peripheral I/O devices and main memory without routing data through the CPU.

• RAID (Redundant Array of Independent Disks): Organizes multiple secondary disk drives into arrays using striping, mirroring, or parity checking to achieve enhanced data reliability, fault tolerance, and high I/O throughput.