Processor Datapath

AI version of Notes

This source is a transcript of a lecture recording by Dr. Ado, primarily focusing on the MIPS Single-Cycle Data Path, the role of the Control Unit, and how various instructions are processed through the hardware.

The following key concepts were discussed:

Logistics and Course Progress

The course is in Week 14, and the curriculum is approximately four weeks behind.
Due to time constraints, the Final Exam will not cover Performance or Memory Hierarchy.
The remainder of the semester will be dedicated to the Data Path and Pipelining.

Data Path Components and Logic

Multiplexers (MUX): These act as selection devices, similar to "if" or "switch" statements in programming. They are used to choose between different data paths (e.g., deciding between $PC + 4$ or a branch target address) based on blue selector signals.
Arithmetic Logic Unit (ALU): A combinational circuit that takes two 32-bit inputs and produces a 32-bit result, along with 1-bit flags for Zero and Overflow.
Registers: MIPS uses a 5-bit register selector because there are 32 registers ($2^5=32$). Registers require an explicit write enable flag if they are not updated on every clock cycle.
Memory: While MIPS conceptually uses unified memory, it functionally accesses separate instruction and data caches to allow simultaneous fetching and data access.

Control Unit and Signals

The control unit’s primary job is to set flags (modeled as a struct in the class assignment) based on the instruction's op-code. Dr. Ado suggests thinking of these signals as answers to specific questions:

RegDst: Is this an R-type instruction? If so, it selects the third register field (rd) as the destination; otherwise, it uses the second field (rt).
ALUSrc: Is the second ALU operand a sign-extended constant (immediate value)?.
MemtoReg: Is the data being written to a register coming from memory (like a load instruction) or the ALU?.
Branch/Jump: Are we departing from the normal sequential instruction flow?.

Instruction Processing

R-type: Reads two registers, performs an ALU operation (determined by the function code), and writes the result back to a register.
I-type (Immediate): Replaces one register operand with a 16-bit constant that must be sign-extended to 32 bits to match the ALU input width.
Branching: Uses the ALU to subtract two register values; if the Zero flag is 1, the values are equal, and the branch is taken. The target address is calculated as $(PC + 4) + (\text{offset} \times 4)$.
Jumping: Replaces the PC with a 32-bit address formed by concatenating the first four bits of the current PC with a 26-bit offset shifted left by two.

Single-Cycle vs. Pipelining

In a single-cycle data path, every instruction executes in exactly one clock cycle. This simplifies conceptual understanding but ignores physical constraints like signal propagation latency.
Pipelining (to be covered next) breaks instructions into multiple stages (likely five) across several clock cycles to improve performance and allow for parallel processing.

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Implementing Jumps