Semiconductor Diode Capacitance, Rectifier Analysis, and BJT Biasing

Forward-Biased Diode Current and Diffusion Capacitance

Shockley Diode Equation:
- The current flowing through a forward-biased p-n junction diode is governed by the Shockley ideal diode equation: $I = I_s \left( e^{\frac{q V}{\eta k T}} - 1 \right)$
- $I$ : Forward diode current in amperes ( $\text{A}$
- $I_s$ : Reverse saturation current in amperes ( $\text{A}$
- $q$ : Elementary electric charge ( $1.6 \times 10^{-19}\,\text{C}$
- $V$ : Applied forward-bias voltage across the diode in volts ( $\text{V}$
- $k$ : Boltzmann constant ( $1.38 \times 10^{-23}\,\text{J/K}$
- $T$ : Absolute temperature in kelvin ( $\text{K}$
- $\eta$ : Ideality factor (emission coefficient), where $\eta = 1$ for an ideal silicon diode under typical conditions.
Forward Current Calculation at Room Temperature:
- Operating Parameters:
  - Semiconductor material: Silicon ( $\text{Si}$
  - Temperature: $T = 300\,\text{K}$
  - Forward-bias voltage: $V = 0.7\,\text{V}$
  - Ideality factor: $\eta = 1$
  - Saturation current: $I_s = 1 \times 10^{-14}\,\text{A}$
  - Minority carrier lifetime: $\tau = 1\,\mu\text{s} = 1 \times 10^{-6}\,\text{s}$
  - Elementary charge: $q = 1.6 \times 10^{-19}\,\text{C}$
  - Boltzmann constant: $k = 1.38 \times 10^{-23}\,\text{J/K}$
- Thermal Voltage Evaluation: $V_T = \frac{k T}{q}$ $V_T = \frac{1.38 \times 10^{-23}\,\text{J/K} \times 300\,\text{K}}{1.6 \times 10^{-19}\,\text{C}} = 0.025875\,\text{V} \approx 25.9\,\text{mV}$
- Diode Current Substitution: $I = 10^{-14} \left( e^{\frac{1.6 \times 10^{-19} \times 0.7}{1.38 \times 10^{-23} \times 300}} - 1 \right)$ $I = 10^{-14} \left( e^{27.053} - 1 \right)$ $I = 0.00561\,\text{A}$ $I = 5.61\,\text{mA}$
Diffusion Capacitance ( $C_D$ ):
- Diffusion capacitance arises from the rearrangement of minority carrier charges stored in the neutral quasi-neutral regions outside the depletion layer under forward-bias conditions.
- Governing Formulations: $C_D = \frac{\tau I}{\eta V_T}$ $C_D = \frac{\tau I}{\eta \left( \frac{k T}{q} \right)}$ $C_D = \frac{q \tau I}{\eta k T}$
- Numerical Substitution: $C_D = \frac{1.6 \times 10^{-19}\,\text{C} \times 1 \times 10^{-6}\,\text{s} \times 0.00561\,\text{A}}{1 \times 1.38 \times 10^{-23}\,\text{J/K} \times 300\,\text{K}}$ $C_D = \frac{8.976 \times 10^{-28}}{4.14 \times 10^{-21}}$ $C_D = 2.17 \times 10^{-7}\,\text{F}$ $C_D = 217\,\text{nF}$

Reverse-Biased Diode Transition Capacitance and Depletion Width

Physical Principles of Transition Capacitance:
- Under reverse-bias conditions, the transition capacitance ( $C_t$ ), also termed depletion-layer or junction capacitance, dominates over diffusion capacitance.
- The reverse voltage widens the space-charge (depletion) region, which acts as a dielectric separating the two conducting p and n semiconductor regions.
Unit Conversion and Silicon Permittivity:
- Doping concentration conversion from $\text{cm}^{-3}$ to $\text{m}^{-3}$ : $N = 1 \times 10^{16}\,\text{cm}^{-3} = 1 \times 10^{22}\,\text{m}^{-3}$
- Permittivity of silicon ( $\epsilon$ $\epsilon = \epsilon_r \times \epsilon_0$ $\epsilon = 11.7 \times 8.85 \times 10^{-12}\,\text{F/m}$ $\epsilon = 1.03645 \times 10^{-10}\,\text{F/m}$
Depletion Region Width ( $W$ ):
- Analytical Formula: $W = \sqrt{\frac{2 \epsilon (V_{bi} + V)}{q N}}$
- Parameters:
  - Elementary charge: $q = 1.6 \times 10^{-19}\,\text{C}$
  - Built-in barrier potential: $V_{bi} = 0.7\,\text{V}$
  - Applied reverse voltage: $V = 5\,\text{V}$
  - Total junction potential: $V_{bi} + V = 0.7\,\text{V} + 5\,\text{V} = 5.7\,\text{V}$
- Evaluation: $W = \sqrt{\frac{2 \times 1.03645 \times 10^{-10}\,\text{F/m} \times 5.7\,\text{V}}{1.6 \times 10^{-19}\,\text{C} \times 1 \times 10^{22}\,\text{m}^{-3}}}$ $W = \sqrt{7.386365625 \times 10^{-9}}$ $W = 8.60 \times 10^{-5}\,\text{m}$
Transition Capacitance ( $C_t$ ) Calculation:
- Capacitance Formula: $C_t = \frac{\epsilon A}{W}$
- Parameters:
  - Cross-sectional junction area: $A = 1 \times 10^{-6}\,\text{m}^2$
  - Permittivity: $\epsilon = 1.03645 \times 10^{-10}\,\text{F/m}$
  - Depletion layer width: $W = 8.60 \times 10^{-5}\,\text{m}$
- Evaluation: $C_t = \frac{1.03645 \times 10^{-10}\,\text{F/m} \times 1 \times 10^{-6}\,\text{m}^2}{8.60 \times 10^{-5}\,\text{m}}$ $C_t = 1.205 \times 10^{-12}\,\text{F}$ $C_t = 1.205\,\text{pF}$

Full-Wave Rectifier Analysis with Resistive Load and Diode Resistance

Circuit Parameters and Operating Conditions:
- Load resistance (purely resistive): $R_L = 5000\,\Omega$
- Diode forward dynamic resistance: $R_f = 400\,\Omega$
- Total series circuit loop resistance: $R_L + R_f = 5000\,\Omega + 400\,\Omega = 5400\,\Omega$
- Input AC voltage function: $V = V_m \sin(2\pi f t) = 200 \sin(2\pi \times 50 t)\,\text{V}$
- Peak input voltage: $V_m = 200\,\text{V}$
- Supply frequency: $f = 50\,\text{Hz}$
Maximum Peak Current ( $I_m$ ):
- Determined by applying Ohm's law to the peak secondary voltage across the conducting loop: $I_m = \frac{V_m}{R_L + R_f}$ $I_m = \frac{200\,\text{V}}{(5000 + 400)\,\Omega} = \frac{200\,\text{V}}{5400\,\Omega}$ $I_m = 0.03704\,\text{A} = 37.04\,\text{mA}$
Average DC Load Current ( $I_{dc}$ ):
- Calculated across a full-wave rectified cycle: $I_{dc} = \frac{2 I_m}{\pi}$ $I_{dc} = \frac{2 \times 0.037\,\text{A}}{3.14} = 0.0236\,\text{A} = 23.6\,\text{mA}$
Root-Mean-Square Current ( $I_{rms}$ ):
- For a sinusoidal full-wave waveform: $I_{rms} = \frac{I_m}{\sqrt{2}}$ $I_{rms} = \frac{0.037\,\text{A}}{\sqrt{2}} = 0.0262\,\text{A} = 26.2\,\text{mA}$
DC Output Power ( $P_{dc}$ ):
- The power delivered to the resistive load $R_L$ by the average direct current: $P_{dc} = (I_{dc})^2 R_L$ $P_{dc} = (0.0236\,\text{A})^2 \times 5000\,\Omega$ $P_{dc} = 0.00055696\,\text{A}^2 \times 5000\,\Omega = 2.8\,\text{W}$
Total AC Input Power ( $P_{ac}$ ):
- The total power supplied by the source delivering current through both the diode forward resistance and the load resistor: $P_{ac} = (I_{rms})^2 (R_L + R_f)$ $P_{ac} = (0.0262\,\text{A})^2 \times 5400\,\Omega$ $P_{ac} = 0.00068644\,\text{A}^2 \times 5400\,\Omega = 3.7\,\text{W}$
Rectification Efficiency ( $\eta$ ):
- The ratio of DC output power to AC input power: $\eta = \frac{(P_{dc})_{out}}{(P_{ac})_{in}} \times 100\%$ $\eta = \frac{2.8\,\text{W}}{3.7\,\text{W}} \times 100\% = 75.7\%$
Ripple Factor ( $r$ ):
- A measure of the residual AC component in the rectified output: $r = \sqrt{\left( \frac{I_{rms}}{I_{dc}} \right)^2 - 1}$ $r = \sqrt{\left( \frac{0.0262\,\text{A}}{0.0236\,\text{A}} \right)^2 - 1}$ $r = \sqrt{(1.11017)^2 - 1} = \sqrt{1.2325 - 1} = \sqrt{0.2325}$ $r = 0.48$

Full-Wave Bridge Rectifier Circuit with Capacitor Filter and Ripple Calculations

Bridge Rectifier Topography and Components:

Full-Wave Bridge Rectifier Circuit with Capacitor Filter

*   The bridge configuration utilizes four diodes arranged in a closed loop, an input step-down center-tapped or standard transformer, a parallel capacitive filter ( $C = 470\,\mu\text{F}$ , and a resistive load ( $R_L = 220\,\Omega$ 
*   During the positive half-cycle of secondary voltage, two opposite diodes conduct simultaneously while the alternate pair is reverse-biased.
*   During the negative half-cycle, the conducting roles swap, maintaining unidirectional current through the load resistance.

Filter Ripple Factor and Output Characteristics:
- Peak secondary output voltage: $V_m = 30\,\text{V}$
- The ripple factor for a rectifier with a shunt filter capacitor is approximated by: $r \approx \frac{1}{2 \sqrt{3} f_r R_L C} = \frac{T_r}{2 \sqrt{3} R_L C}$
- For a full-wave rectifier, ripple frequency is double the line frequency ( $f_r = 2 f$
- Alternative peak-to-peak approximation relation: $r = \frac{V_{r(p-p)}}{2 \sqrt{3} V_{dc}}$
Capacitor Sizing Under Defined Ripple Constraints:
- Design Criteria:
  - Supply frequency: $f = 50\,\text{Hz}$
  - DC load voltage: $V_{dc} = 12\,\text{V}$
  - Load current: $I_{dc} = 10\,\text{mA} = 10 \times 10^{-3}\,\text{A}$
  - Maximum allowable ripple factor: $r = 4\% = 0.04$
- Filter Capacitor Calculation:
  - Using the peak-to-peak ripple voltage constraint $V_r = r \times V_{dc}$ : $V_r = 0.04 \times 12\,\text{V} = 0.48\,\text{V}$
  - Evaluating the capacitance required to limit discharge voltage droop: $C \ge \frac{I_{dc}}{f \times V_r}$ $C \ge \frac{10 \times 10^{-3}\,\text{A}}{50\,\text{Hz} \times 0.48\,\text{V}}$ $C \ge \frac{0.01}{24} = 0.41667 \times 10^{-3}\,\text{F}$ $C \ge 416.67\,\mu\text{F}$

BJT Common-Emitter DC Load Line and Q-Point Operating Analysis

Common-Emitter Circuit Configuration and DC Load Line:

2N4401 BJT Circuit Schematic and DC Load Line with Q-Point

*   The circuit features an NPN transistor (part number 2N4401) configured in a common-emitter mode with an adjustable base resistor  $R_B$ , a fixed collector resistance  $R_C = 1.5\,\text{k}\Omega$ , and a positive DC collector voltage supply  $V_{CC} = +30\,\text{V}$ .

DC Load Line Equations:
- Applying Kirchhoff's Voltage Law (KVL) around the collector-emitter circuit: $V_{CC} - I_C R_C - V_{CE} = 0$ $V_{CE} = V_{CC} - I_C R_C$
- **Cutoff Point ( $I_C = 0$ $V_{CE(\text{cutoff})} = V_{CC} = 30\,\text{V}$
  - The horizontal intercept on the output characteristic graph is located at $(30\,\text{V}, 0\,\text{mA})$ .
- **Saturation Point ( $V_{CE} = 0$ $I_{C(\text{sat})} = \frac{V_{CC}}{R_C}$ $I_{C(\text{sat})} = \frac{30\,\text{V}}{1.5\,\text{k}\Omega} = \frac{30\,\text{V}}{1500\,\Omega} = 20\,\text{mA}$
  - The vertical intercept on the output characteristic graph is located at $(0\,\text{V}, 20\,\text{mA})$ .
Quiescent Operating Point (Q-Point) Evaluation:
- From the continuous DC load line curve, point $Q$ is situated at: $V_{CEQ} = 21\,\text{V}$ $I_{CQ} = 6\,\text{mA}$
- Verification Using Loop Equations: $V_{CE} = 30\,\text{V} - (6\,\text{mA} \times 1.5\,\text{k}\Omega) = 30\,\text{V} - 9\,\text{V} = 21\,\text{V}$
Base Current and Base Resistor Calculations at Q-Point:
- DC Current Gain: $\beta_{dc} = 80$
- **Base Current ( $I_B$ $I_B = \frac{I_C}{\beta_{dc}}$ $I_B = \frac{6\,\text{mA}}{80} = 0.075\,\text{mA} = 75\,\mu\text{A}$
- Base Circuit Analysis:
  - Assuming a standard silicon base-emitter junction drop: $V_{BE} = 0.7\,\text{V}$
  - Applying KVL to the base loop: $V_{CC} - I_B R_B - V_{BE} = 0$ $R_B = \frac{V_{CC} - V_{BE}}{I_B}$ $R_B = \frac{30\,\text{V} - 0.7\,\text{V}}{75 \times 10^{-6}\,\text{A}} = \frac{29.3\,\text{V}}{75 \times 10^{-6}\,\text{A}} \approx 390.67\,\text{k}\Omega$