Chapter 4 - The Processor Notes

Introduction to the Processor

  • Covers CPU performance factors including:
    • Instruction Count: Determined by ISA (Instruction Set Architecture) and compiler.
    • CPI (Cycles per Instruction) and Cycle Time: Determined by CPU hardware.
  • Examines two MIPS (Microprocessor without Interlocked Pipeline Stages) implementations:
    • A simplified version.
    • A more realistic pipelined version.

Instruction Execution Process

  • Steps in executing an instruction:
    1. PC (Program Counter) fetches instruction from memory.
    2. Reads registers specified by the instruction from the register file.
    3. Depending on the type of instruction, the ALU (Arithmetic Logic Unit) may:
    • Calculate arithmetic results.
    • Compute addresses for load/store instructions.
    • Determine branch target addresses.
    1. Access data memory as needed for load/store actions.
    2. Update the PC with either the target address (for branches) or the next instruction address (PC + 4).

Multiplexers in CPU Design

  • Multiplexers: Necessary for routing data signals to the correct components.
  • Cannot simply connect wires; multiplexers are used to select between different input sources.

Basic Logic Design Concepts

  • Information is encoded in binary; low voltage = 0, high voltage = 1.
  • One wire per bit or multi-bit data on buses.
  • Types of elements:
    • Combinational Elements: Operate on data and produce outputs based on inputs (e.g., AND gates, multiplexers).
    • Sequential Elements: Store data in circuits (e.g., registers using clock signals).

Clocking Methodology

  • Combinational logic processes data during clock cycles.
  • Longest delay determines the clock period.

Building the Datapath

  • Datapath: Composed of elements that process data and addresses within the CPU (e.g., registers, ALUs, and memories).
  • The design is refined incrementally to optimize functionality.

Instruction Types in MIPS

  1. R-Format Instructions: Read two register operands and perform arithmetic/logical operations.
    • Example: add $t1, $t2, $t3
  2. Load/Store Instructions: Read register operands and calculate addresses using offsets.
    • Example: lw $t1, offset($t2) (load word)
    • Example: sw $t1, offset($t2) (store word)
  3. Branch Instructions: Compare operands and calculate target addresses based on conditions.
    • Example: beq $t1, $t2, offset

Datapath with Control Signal Generation

  • The control unit generates signals based on the instruction type, directing the flow of data through the datapath.

Pipelining Overview

  • Pipelining splits instruction processing into multiple stages:
    1. IF: Instruction Fetch
    2. ID: Instruction Decode & Register Read
    3. EX: Execute or calculate address
    4. MEM: Memory Access
    5. WB: Write Back to register
  • Significant speedup in CPU throughput due to overlapping execution of instructions.

Pipeline Performance and Hazards

  • Pipeline Hazards: Can stall instruction execution and may arise from:
    • Structural hazards (resource conflicts)
    • Data hazards (dependencies on previous instructions)
    • Control hazards (branching decisions not resolved)
  • Solutions include forwarding (bypassing) data and introducing stalls/bubbles in the pipeline.

Branch Prediction Techniques

  • Static and Dynamic Branch Prediction:
    • Static: Based on program behavior (e.g., loops).
    • Dynamic: Utilizes hardware to learn and predict branch behavior based on execution history.
  • Branch Target Buffer: A cache to hold predicted branch targets, allowing quick fetch if predictions are correct.

Exceptions and Interrupts Management

  • Exception: Error internally generated, requiring change in control flow (e.g., overflow).
  • Interrupt: Triggered by external events (e.g., I/O devices).
  • MIPS utilizes a System Control Coprocessor (CP0) to manage exceptions, saving necessary state and jumping to handler routines accordingly.

Instruction-Level Parallelism (ILP)

  • Utilizes pipelining to improve the execution of multiple instructions simultaneously, enhancing CPU performance but challenged by inherent data dependencies.
  • Techniques for increased ILP include deeper pipelines and dynamic scheduling of instructions.

Conclusion

  • Effective CPU design hinges on ISA and control integration, with pipelining improving throughput but requiring careful management of hazards and dependencies.