Programmable Keyboard / Display Controller – Intel 8279

Intel 8279 = general-purpose Keyboard/Display Controller (KDC)
- Simultaneously scans a keyboard matrix, debounces & encodes key data, and refreshes a multiplexed display.
- Acts as a dedicated hardware coprocessor → frees the main CPU (e.g.
  $8085$ / $8086$ ) from cyclic polling & display-refresh chores.
Typical system chain:
- User presses key → 8279 detects closure, debounces, places key-code in FIFO, optionally raises $\text{IRQ}$ → CPU reads code when convenient.
- CPU writes character/segment data to Display RAM → 8279 automatically multiplexes data onto OUT lines synchronised with scan lines.

Hardware approach (dedicated peripheral such as 8279)
- Pros: CPU time saved, consistent timing, built-in debounce, FIFO, display blanking, scalable up to $64$ keys / $16$ digits.
- Cons: Added silicon cost.
Software approach (bit-bang via PPI)
- CPU continuously loops through rows & columns, AND refreshes display → large interrupt latency & high firmware complexity.

40-pin LSI IC; interfaces directly to $8085$ / $8086$ buses.
Keyboard support
- Matrix up to $8\times8 = 64$ keys.
- Selectable key-resolution schemes:
  • 2-key lockout (ignores all but the first of concurrent presses)
  • N-key rollover (records every simultaneous press in order)
Display support
- Up to $16$ multiplexed characters (7-segment, alphanumeric, or dot-matrix rows).
- 16-byte Display RAM; automatic refresh & inhibit/blanking control.
Built-in debounce (~ $10\text{ ms}$ per key) & keyboard FIFO (8×8-bit).
Programmability
- Three input modes (Scanned Keyboard, Scanned Sensor, Strobed Input).
- Two output modes (Left Entry vs Right Entry).
- Encoded vs Decoded scan, blanking, clock prescale, etc.
Interrupt output $\text{IRQ}$ asserts when FIFO not empty.

Data Buffers (DB7–DB0)
- Bi-directional; carry data, command, status.
I/O Control Logic
- Signals: $A0$ (addr), $CS$ (chip select), $RD$ , $WR$ .
- Truth table (summary):
  • $A0=0,\, RD=0 \Rightarrow$ CPU reads data.
  • $A0=0,\, WR=0 \Rightarrow$ CPU writes data.
  • $A0=1,\, RD=0 \Rightarrow$ CPU reads status.
  • $A0=1,\, WR=0 \Rightarrow$ CPU writes command.
Control & Timing Registers
- Latch keyboard/display modes on $WR$ rising edge when $A0=1$ .
Timing & Control Chain
- External $CLK$ prescaled to $100\,\text{kHz}$ internal core clock.
- Generates scan windows, debounce delays, display multiplex period.
- Requires external clock > $200\,\text{kHz}$ to preserve spec timings.

Scan Counter + Lines $SL3!:!SL0$
- Provide row (keyboard) / digit (display) select.
- Two programmable formats:
  • Encoded Mode → binary count $0000\rightarrow1111$ (active-high), needs external 4→16 decoder (keyboard uses 8 of 16).
  • Decoded Mode → internal 2-bit decoder yields 4 active-low patterns $1110,1101,1011,0111$ → direct drive of 4-digit display or 8×4 keyboard.

Return Buffers $RL7!:!RL0$ + special inputs
- Connected to keyboard columns; internal pull-ups → idle HIGH, switch closure → LOW.
- $SHIFT$ line & $CNTL/STB$ line latched with key code for meta-key status.
Keyboard Debounce & Control
- Monitors closure for ~ $10\text{ ms}$ ; if steady, forms 8-bit word: $[SHIFT, CNTL, Row(3), Col(4)]$ → writes to FIFO.
- Generates $\text{IRQ}$ whenever FIFO non-empty.
FIFO / Sensor RAM (8×8)
- Dual-mode: queue of key codes OR static sensor bitmap (in Sensor Matrix mode).
- RAM status flags: FULL, EMPTY, #characters.

16×8 Display RAM
- Indexed by current scan count; holds segment/row patterns for each digit.
Display Address Registers
- Auto-increment/return-home according to Left/Right Entry rules.
Output Lines
- $OUTB3!:!OUTB0$ and $OUTA3!:!OUTA0$ organised as one 8-bit port or two 4-bit ports.
- Data emitted in sync with scan lines (digit 0 ↔ scan "0000", … digit 15 ↔ scan "1111").
- Independent blanking; global blank via $BD$ (active-low).

CPU Interface (DB7–0, RD, WR, A0, CS, RESET, CLK, IRQ)
- $RESET$ places device in default: 16×8 left-entry display, two-key lockout.
Keyboard Data (RL7–0, SHIFT, CNTL/STB)
- In Strobed Input mode, rising edge on CNTL/STB captures RL data into FIFO.
Display Data (OUTA3–0, OUTB3–0, BD)
Scan Lines (SL3–0)

Scanned Keyboard Mode
- Encoded or Decoded scanning; supports 2-key lockout/N-key rollover.
Scanned Sensor Matrix Mode
- FIFO behaves as 8×8 switch map; polling alternative for static sensors.
Strobed Input Mode
- External strobe (CNTL/STB ↑) dumps RL7–0 into FIFO instantaneously.

Left Entry (typewriter style): new characters appear at left-most register and shift rightward on subsequent entries.
Right Entry (calculator style): new characters appear at right end and push existing ones left.

8279 still used in training kits, industrial HMIs, elevator panels.
Debounce hardware avoids software race conditions & long ISRs.
FIFO together with $\text{IRQ}$ provides event-driven design paradigm → CPU can sleep until human input detected.
Cost factor vs modern microcontrollers with integrated GPIO & timers is an economic/legacy trade-off.
Ethical implication: reliable human-machine interface critical in safety devices; hardware debounce ensures deterministic behaviour.

Active-LOW pins: $RD, WR, CS, BD, SLx$ (decoded), $RESET$ (HIGH), $IRQ$ (LOW when asserted).
Clock: any TTL square wave > $200\,\text{kHz}$ ; internally prescaled to $100\,\text{kHz}$ .
FIFO depth: $8$ ; status flags readable via status word ( $A0=1, RD=0$ ).

Differentiate 2-key lockout vs N-key rollover.
Explain encoded vs decoded scan with timing diagrams.
Draw & annotate pin diagram; specify which pins connect to 7-segment common anode driver.
Calculate debounce time if internal clock scaled to $100\,\text{kHz}$ .
Describe how 8279 reduces CPU overhead compared to software approach.

“8279 = 8×8 keyboard, 2×4 output ports, 7-segment 9 (display) –> mnemonic 8279.”
LEFT = Typewriter (LTR), RIGHT = CalculatoR (RTR) – first letters line up.