Computer System Structure and Hardware Fundamentals

Computer System Operation and Bus Architecture

• System Interconnection and Concurrency:
  • The Central Processing Unit ($\text{CPU}$) and multiple device controllers are connected through shared communication pathways known as common buses.
  • The common system bus comprises three distinct functional components:
  • Data Bus: Carries the actual binary data transferred between components.
  • Address Bus: Transmits physical memory addresses that the $\text{CPU}$ or controllers need to access.
  • Control Bus: Transmits operational signals, read/write commands, clock synchronization pulses, and status indicators.
  • The $\text{CPU}$ and peripheral device controllers operate concurrently, executing instructions and managing device operations in parallel.
  • A dedicated Memory Controller arbitrates and synchronizes access to shared physical memory ($\text{RAM}$) to ensure data coherence and prevent concurrent access conflicts.

• Device Controller Architecture:
  • Each individual device controller is dedicated to managing a specific class or peripheral category of hardware (e.g., hard disk controller, printer controller, tape drive controller).
  • A single controller can oversee one or multiple physical devices.
  • Every controller maintains an integrated local buffer storage of varying size to temporarily hold data during transfer.
  • Communication between the processor and device controllers involves moving data from and to main memory to and from these local buffers under software or direct control.
  • Upon finishing a data transfer or operational sequence, the device controller signals completion to the $\text{CPU}$ by generating a hardware interrupt.

Bootstrap Sequence and System Startup

• Phase 1: Hardware Power-Up:

  • Electrical power is supplied to the motherboard, triggering internal initialization circuits and resetting $\text{CPU}$ registers to predefined baseline states.

• Phase 2: Execution of Bootstrap Program:

  • The initial system startup program, known as the bootstrap, is permanently held in non-volatile Read-Only Memory ($\text{ROM}$) or Electrically Erasable Programmable Read-Only Memory ($\text{EEPROM}$).
  • The bootstrap code performs comprehensive low-level hardware diagnostics and initialization, specifically:
  1. Initializes internal $\text{CPU}$ registers.
  2. Initializes and configures attached device controllers.
  3. Initializes system memory contents.
  4. Locates, verifies, and loads the operating system kernel into main memory.

• Phase 3: Kernel Execution and Init Process:

  • Execution control transfers from the bootstrap loader to the operating system kernel entry point.
  • The kernel mounts the root filesystem, initializes core subsystems, and spawns the initial user-space process, designated as init.

• Phase 4: Event-Driven Waiting State:

  • Once initial user services are running, the system enters an idle state where the init process and system threads wait passively for external events (interrupts) to occur.

Interrupt Architecture and Handling Mechanics

• Interrupt Fundamentals:

  • An interrupt is an asynchronous electrical or software signal delivered directly to the $\text{CPU}$ indicating that an event requires immediate processor attention.
  • Modern operating systems are architecturally interrupt-driven; if there are no processes to execute, no I/O operations pending, and no user inputs, the operating system remains idle waiting for interrupts.

• Interrupt Vectoring:

  • The $\text{CPU}$ determines the appropriate routine to execute by querying an Interrupt Vector table.
  • The interrupt vector is an indexed memory array that stores the memory addresses of all specific Interrupt Service Routines ($\text{ISRs}$).
  • Direct indexing via the interrupt vector minimizes the lookup latency required to dispatch service routines.

• Classification of Interrupts:

  • Hardware Interrupts: Signals transmitted through hardware lines directly from peripheral controllers or external pins (e.g., disk read complete, network packet arrival, timer ticks).
  • Software Interrupts (Traps): Programmatically generated conditions originating within the $\text{CPU}$ itself:
  • Errors: Abnormal execution conditions such as division by zero ($\frac{x}{0}$) or unauthorized memory access violations.
  • System Requests (System Calls): Deliberate requests from user applications invoking protected operating system services (e.g., file input/output, process creation).

• Step-by-Step Interrupt Handling Sequence:

  1. Signal Reception: The $\text{CPU}$ hardware detects the asserted interrupt line.
  2. Suspension of Current Task: The $\text{CPU}$ suspends execution of the currently running instruction sequence.
  3. State Preservation: The architecture stores critical state data—including the program counter, processor status words, and register contents—onto the system execution stack.
  4. Vector Lookup and Transfer: Execution vectors to a predetermined, fixed memory address containing the appropriate Interrupt Service Routine ($\text{ISR}$).
  5. Execution of Handler: The $\text{CPU}$ executes the $\text{ISR}$ to satisfy the peripheral or software request.
  6. Process Resumption: Upon handler completion, stored machine registers and the program counter are restored, enabling the interrupted process to resume seamlessly.

• Critical Constraints on Interrupts:

  • Handlers must be constructed to complete execution with minimal latency to prevent dropping incoming subsequent interrupts.
  • Total state preservation is mandatory; any register alteration uncommitted prior to resumption compromises program determinism.

Input/Output Structure and Transfer Modes

• Controller Operations:

  • The controller handles low-level bit manipulation and physical signaling for a specific device type.
  • It facilitates bi-directional data transfers between device-level media and its internal local buffer.
  • Buffer capacities vary widely depending on device bandwidth and transfer unit sizes.

• Comparison of I/O Execution Methods:

  • Synchronous I/O:
  • A user process issues an I/O request via a system call.
  • The operating system device driver starts the physical I/O operation.
  • The calling process enters a waiting (blocked) state, relinquishing the $\text{CPU}$.
  • The hardware executes the data transfer.
  • Once the transfer completes, an interrupt is raised to awaken the waiting process.
  • Control returns to the user process only after the data is fully available.
  • Asynchronous I/O:
  • A user process initiates an I/O request.
  • The device driver schedules and initiates the hardware operation.
  • Control returns immediately to the calling user process without forcing it to wait.
  • The physical I/O continues concurrently alongside general system computation.
  • When transfer finishes, an interrupt alerts the operating system to process the completed transfer and deliver notification to the requesting application.

Direct Memory Access (DMA)

• Functional Role and Purpose:

  • Designed specifically for high-speed I/O peripheral controllers capable of moving information at throughput rates approaching main memory bus limits.
  • Avoids processor degradation caused by programmed I/O, where every data byte requires $\text{CPU}$ intervention.

• Transfer Protocol:

  • The device controller directly arbitrates for bus control and streams entire contiguous blocks of data directly from its local buffer into main system memory (or vice-versa) completely bypassing intermediate $\text{CPU}$ staging.
  • The $\text{CPU}$ initiates the process by writing memory addresses, byte counts, and transfer direction to controller registers, then shifts attention to other tasks.

• Interrupt Reduction:

  • Under standard programmed I/O, one interrupt is triggered per byte or word transferred.
  • Under $\text{DMA}$, exactly one interrupt is generated per entire block, reducing $\text{CPU}$ context switching overhead.

Storage Structure and Memory Hierarchy

• Primary vs. Secondary Storage Divisions:

  • Main Memory ($\text{RAM}$): The only large storage medium that the $\text{CPU}$ instruction pipeline can read and write to directly via system buses; it is inherently volatile and loses stored data upon power termination.
  • Secondary Storage: Serves as a non-volatile, high-capacity extension of primary memory designed to permanently store arbitrary user data, software programs, and operating system images.

• Storage-Device Hierarchy:

  • Storage systems are organized hierarchically based on access latency, dollar cost per unit of storage, and overall capacity.
  • Data progression from fastest, highest cost, lowest capacity (top) down to slowest, lowest cost, largest capacity (bottom):
  1. Registers: Located within the $\text{CPU}$ core; cycle times matching the processor clock.
  2. Cache: High-speed Static $\text{RAM}$ ($\text{SRAM}$) staged close to processor cores to hold frequently referenced instructions and data blocks.
  3. Main Memory: Dynamic $\text{RAM}$ ($\text{DRAM}$) holding active execution images.
  4. Electronic Disk: Non-volatile solid-state drives ($\text{SSD}$) and flash memory.
  5. Magnetic Disk: Rigid mechanical platters providing traditional secondary file storage.
  6. Optical Disk: Storage media read and written via focused laser optics (e.g., $\text{CD}$, $\text{DVD}$, $\text{Blu-ray}$).
  7. Magnetic Tapes: Sequential ribbon storage for long-term data archiving.

• Evaluation Factors Across Storage Technologies:

  • Speed: Read/write access times and sequential throughput bandwidth.
  • Cost: Monetary expense calculated per unit byte or gigabyte.
  • Capacity: Maximum volumetric storage allowance.
  • Volatility: Retention capability in the absence of continuous electrical current.
  • Reliability: Mean time between failures ($\text{MTBF}$) and error resilience.
  • Portability: Ease of physical detachment, transportation, and mounting across diverse host environments.

• Random Access Memory (RAM) Organization:

  • Structured as an ordered, indexed array of memory words.
  • Each individual byte possesses a distinct address identifier.
  • Address representation bifurcates into:
  • Physical Addresses: The hardware locations mapped to the physical memory chips.
  • Logical Addresses: The abstract memory space generated by the $\text{CPU}$ during instruction execution.
  • Core $\text{CPU}$ memory operations:
  • Load: Reads a word from a designated main memory address into an internal $\text{CPU}$ register.
  • Store: Transfers a word from a designated $\text{CPU}$ register into a specified main memory location.

Mass-Storage Devices: Magnetic Disks and Tapes

• Magnetic Disk Architecture and Geometry:
  • Constructed using rigid circular platters made of metal alloys or glass, coated on both surfaces with thin magnetic recording material.
  • Platters are mounted on a central rotating spindle that turns at high speeds.
  • Logical surface division:
  • Tracks: Concentric circular rings mapped out across each platter surface.
  • Sectors: Fixed-size angular segments into which each track is subdivided.
  • Cylinder: The vertical alignment of tracks across all platter surfaces located at a specific radial distance from the spindle.
  • Mechanical Head Assembly:
  • Read-write heads float aerodynamically over the platter surfaces on microscopic air cushions.
  • Heads attach to an actuator arm assembly that shifts radially across the disk surfaces to align with target cylinders.
  • The Disk Controller coordinates physical actuator positioning, read/write conversions, and logical translation between peripheral sectors and standard computer blocks.

• Magnetic Tapes:
  • Formed the primary medium for early secondary computer storage systems.
  • Access mechanism is purely sequential rather than random, resulting in slow read/write access times when accessing non-contiguous records.
  • Modern functional roles:
  • System backup and cold disaster recovery pipelines.
  • Archival preservation of infrequently referenced enterprise datasets.
  • Common legacy and enterprise cartridge capacities include small ($50\,\text{GB}$), medium ($150\,\text{GB}$), and large ($330\,\text{GB}$) formats, alongside historical tape profiles such as $4\,\text{mm}\;\text{DAT}$.

Hardware Protection and Operating System Integrity

• Evolution of System Protection:

  • Early Systems: Characterized by single-user architectures where the active programmer maintained unfettered, unmediated control over all physical hardware, peripherals, and memory segments.
  • Single-Task Fault Impact: An algorithmic or addressing error in an early system program affected only that specific running application.
  • Multitasking Environments: When concurrent execution was introduced, an uncontrolled bug or malicious routine in one program could corrupt the code, memory boundaries, or I/O access of other resident tasks.
  • Desktop operating environments without enforced boundaries permit unconstrained processes to alter arbitrary memory segments or overwrite external application states.

• Hardware-Enforced Error Management Pipeline:

  • System errors include:
  • Illegal Instructions: Attempting to execute undefined opcodes or privileged kernel operations from user space.
  • Infinite Loops: Unbounded programmatic cycling monopolizing processor bandwidth.
  • Illegal Memory Access: Addressing space beyond allocated process bounds or attempting to read/write another application's memory range.
  • Step-by-step error response sequence:
  1. Detection: Hardware logic monitoring execution identifies a constraint failure (e.g., bounds violation, opcode violation).
  2. Trapping: The hardware immediately generates an internal trap signal, passing operational control to the operating system kernel.
  3. Kernel Processing: The operating system identifies the fault type, records system state diagnostics, and determines intervention policies.
  4. Process Abort: The faulty application process is abruptly terminated to prevent system-wide instability.
  5. Core Dumping: If configured, the operating system dumps the complete memory footprint and register states of the terminated process onto disk storage for offline debugging.

• Three Foundations of Operational Protection:

  • 1. I/O Protection (Dual-Mode Execution):
  • Solves illegal instruction execution and hardware interference.
  • Implemented through architectural modes supported by hardware flags (e.g., mode bit):
    • User Mode: Default execution state for user programs with restricted instruction privileges; direct hardware and I/O instructions are strictly prohibited.
    • System Mode (Kernel Mode / Supervisor Mode / Monitor Mode):
    • Privileged state enabling full hardware and architectural instruction set execution.
    • Transition from User Mode to Kernel Mode occurs strictly via hardware traps or system calls.
  • 2. Memory Protection (Base and Limit Registers):
  • Solves unauthorized memory tampering and segmentation violations.
  • Hardware registers restrict the physical address space accessible to any given program:
    • Base Register: Stores the lowest legal physical memory address allocated to the active process.
    • Limit Register: Stores the exact size or span of the legal address range allocated to the process.
  • Every memory reference dynamically generated by the $\text{CPU}$ is checked against these registers:       $\text{Base} \le \text{Address} < \text{Base} + \text{Limit}$
  • Any attempt to reference memory outside this range raises a hardware addressing trap to the operating system.
  • 3. CPU Protection (Hardware Timers):
  • Prevents runaway programs, infinite loops, and processor hogging.
  • A dedicated hardware timer is programmed to decrement at regular clock intervals.
  • The operating system sets the timer register with a specific quantum before transferring execution control to a user application in user mode.
  • When the counter reaches zero, the timer fires an interrupt.
  • This automatically transfers execution control back to the operating system kernel, enabling the scheduler to context switch the processor to another process.