Unit5

UNIT V: MEMORY & I/O SYSTEMS

1. MEMORY HIERARCHY

  • Definition: A memory hierarchy comprises multiple levels of memory with different speeds and sizes.

  • Characteristics of Memory Hierarchy:

    • Faster memories are typically smaller and more expensive per bit compared to slower memories.

    • Data is copied between only two adjacent levels at a time.

    • The upper level (closer to the processor) is smaller and faster, utilizing more expensive technology.

  • Key Terms:

    • Block: Minimum unit of information that can either be present or absent in the memory hierarchy.

    • Hit: Requested data found in the upper memory level.

    • Miss: Requested data not found in the upper level, prompting access to the lower level.

    • Hit Rate: Fraction of memory accesses found in the upper level (performance metric).

    • Miss Rate: Fraction of memory accesses not found in the upper level (1 - hit rate).

    • Hit Time: Time taken to access the upper level memory including hit/miss determination time.

    • Miss Penalty: Time to retrieve a block from the lower level plus the delivery time to the processor.

2. MEMORY TECHNOLOGY

  • DRAM (Dynamic Random Access Memory):

    • Used for main memory, less costly per bit than SRAM but slower.

    • Requires periodic refreshing due to charge decay.

  • SRAM (Static Random Access Memory):

    • Utilizes multiple transistors per bit, faster and doesn't require refreshing.

    • Commonly used in caches due to speed.

  • Flash Memory:

    • Non-volatile memory used in personal mobile devices.

    • Uses wear leveling to manage write applications and prolong lifespan.

  • Magnetic Disk:

    • Consists of platters rotating at high speeds (5400 to 15000 RPM).

    • Data organized in tracks and sectors, slower access time compared to semiconductors but cheaper per bit.

3. CACHE MEMORY

  • Structure between the processor and main memory, enhances performance by reducing access times.

  • Cache Mapping Techniques:

    • Direct Mapping: Each block maps to one cache location (block address modulo cache size).

    • Fully Associative: A block can be stored in any cache location; offers flexibility at the cost of complexity.

    • Set Associative: Hybrid approach between direct-mapped and fully associative; each block maps to a specific set.

  • Cache Performance Measurements:

    • Hit rate, miss rate, block size, and overall effectiveness assessed by performance metrics.

4. ACCESSING I/O DEVICES

  • Bus: A shared communication link connecting multiple subsystems.

    • Consists of address, data, and control lines.

  • Input/Output System:

    • Memory-Mapped I/O: I/O devices share the same address space as memory.

    • Programmed I/O: CPU directly controls all I/O operations, suitable for simple systems.

5. INTERRUPTS

  • Mechanism for CPU to temporarily transfer control from its current program to an ISR (Interrupt Service Routine).

  • Interrupt Handling Techniques:

    • Maskable and Nonmaskable Interrupts: Control whether interrupts are acknowledged.

    • Daisy Chaining: Devices connected in series, prioritizing based on position.

    • Vectored Interrupts: Assigns unique address to each device interrupt.

6. DIRECT MEMORY ACCESS (DMA)

  • Technique for transferring large blocks of data between external devices and main memory with minimal CPU intervention.

  • DMA Control Process:

    • CPU provides starting address, word count, and control signals to the DMA controller.

    • Initiates data transfer and interrupts CPU upon completion.

7. BUS ARBITRATION

  • Bus Master: Device that initiates data transfers on the bus.

  • Two Types of Bus Arbitration:

    • Centralized Arbitration: One central controller manages bus access.

    • Distributed Arbitration: Each device participates in bus access contention based on its ID, allows greater flexibility.