RISC-V Comprehensive Study Notes

Introduction to RISC-V

Overview of the Lecture Structure

  • Layered Abstractions:

    • High-Level Language Program

    • Assembly Language Program

      • Example Assembly Code:

      • lw x3, 0(x10) (load word from address in x10 to register x3)

      • lw x4, 4(x10) (load word from address in x10 + 4 to register x4)

      • sw x4, 0(x10) (store word in register x4 to address in x10)

      • sw x3, 4(x10) (store word in register x3 to address in x10 + 4)

    • Compiler

    • Machine Language Program (RISC-V)

    • Assembler (Binary representation)

      • Example Binary Code:

      • 1000 1101 1110 0010 0000 0000 0000 0000

      • 1000 1110 0001 0000 0000 0000 0000

      • 0100 1010 1110 0001 0010 0000 0000 0000

      • 0000 1010 1101 1110 0010 0000 0000 0000

Assembly Language Understanding

  • Functionality of a Processor:

    • Executes a series of instructions.

    • Instructions are the primitive operations that a processor can execute.

    • Analogy to a sentence: operations (verbs) applied to operands (objects), processed in sequence.

  • Characteristics of Assembly Language:

    • Instructions represent simple operations (e.g., load from memory, store to memory, arithmetic operations).

    • More complex programming language statements are compiled into primitive operations.

    • Different processors have different Instruction Set Architectures (ISAs).

    • Common ISAs: ARM (mobile devices), Intel x86 (PCs), PowerPC (IBM systems), RISC-V (open-source ISA).

Importance of Learning Assembly

  • Benefits of Understanding Assembly Language:

    • Insight into computer operations.

    • Deeper comprehension than high-level programming languages.

    • Understanding performance implications of different coding approaches.

    • Anecdotal evidence suggests assembly knowledge improves programmer competency.

Trends in Instruction Set Architecture

  • Historical Trends:

    • Early processors: Complex instructions (CISC).

    • Example: Intel x86 architecture.

    • Development of RISC (Reduced Instruction Set Computers):

    • Focus on small and simple instructions for faster hardware implementations.

    • Break down of instructions into steps allows simultaneous instruction processing, enhancing speed.

    • Complex tasks are better handled in software than in hardware.

RISC-V Overview

  • Characteristics of RISC-V:

    • Open-source, license-free ISA specification.

    • Supported by a growing ecosystem of software and hardware.

    • Applicable to all computer systems, from sensors to supercomputers.

    • Variants include 32-bit, 64-bit, 128-bit, and embedded 16-bit instructions.

    • Focus in class: 32-bit variant.

  • RISC-V vs. x86:

    • RISC-V is simpler and more elegant, making it easier to learn and teach.

    • Easier hardware implementation leads to efficiency and explanatory clarity.

    • Encourages understanding across multiple layers of abstraction: instructions, machine language, and hardware implementation.

Challenges with x86

  • Complexity and Intimidation in x86 Architecture.

    • x86 has a more complex set of registers and features that can be overwhelming compared to RISC-V.

RISC-V Applications in Industry

  • Recent Developments:

    • Tenstorrent announced a roadmap for ultra-high-performance RISC-V CPUs and AI accelerators aimed at HPC (High Performance Computing) and AI applications.

    • The versatility of RISC-V in applications like financial simulations, genomic research, and climate modeling.

    • RISC-V's architecture showcases predictable performance and efficiency compared to GPUs for specific tasks.

Instruction Set Structure

  • Assembly Language as Instruction Set Representation:

    • Each line in assembly language denotes one instruction.

    • Example of an instruction: add x10, x11, x12 (adds contents of registers x11 and x12 and stores in x10).

Differences Between High-Level Languages and Assembly

  • High-Level Languages:

    • Variables declared with types and can represent values accordingly.

    • More complex expressions can be expressed in a single line, e.g., a = b * 2 - (a[0] + *p);

  • Assembly Language:

    • Operands consist solely of registers or immediate values.

    • Characteristics: no variable types; registers hold just bits.

    • Operations on registers inform the data type interpretation.

Registers in Processor Architecture

  • Role of Registers:

    • Fundamental component in processor control and data path

    • Fast access (less than 0.25 ns); Directly implemented in hardware.

  • Access Speed:

    • Light travels 10 cm in 0.3 ns; registers are faster than any storage form available.

RISC-V Register Specifications

  • Register Characteristics:

    • RISC-V contains 32 general-purpose registers, each 32 bits wide (for 32-bit variant).

    • Register naming: x0-x31, with x0 always zero.

    • Mnemonic names for convenience: x2 is referred to as sp (stack pointer), and x1 is ra (return address).

Instruction Construction

  • Basic Instruction Structure:

    • Syntax: opname rd, rs1, rs2

      • rd: Destination register

      • rs1 and rs2: Source registers

  • Example Instructions:

    • Addition: add x1, x2, x3 translates to C: a = b + c.

    • Subtraction: sub x4, x5, x6 translates to C: d = e - f.

Instruction Translation Examples

  • Example for Multiple Operations:

    • Translate: a = b + c + d - e

  • Resulting Instructions:

    • add x10, x1, x2 (Calculates b + c)

    • add x10, x10, x3 (Adds d to result)

    • sub x10, x10, x4 (Subtracts e)

Immediate Operands in RISC-V

  • Definition of Immediate Operands:

    • Immediate numbers encoded as signed 12-bit integers within instructions.

    • Example instruction with immediate: addi x3, x4, 10

      • x3 is the destination, x4 is the source, and 10 is the immediate operand.

Subtraction with Immediate Values

  • Subtraction Mechanics:

    • No subi instruction available in RISC-V; subtracting instead uses negative addition: subi x3, x4, 10 effectively translates to addi x3, x4, -10.

Register Zero in RISC-V

  • Special Register Behavior:

    • Register x0 is hardwired to zero, eliminating the need for zero literals in arithmetic operations.

    • Example: add x3, x4, x0 results in f = g;

Knowledge Check Questions

  • Understanding of types associated with variables in C compared to assembly.

    • True/False: Types are associated with declarations in C but with operands in Assembly.

    • Also evaluate RISC-V limitations with respect to compilation for variables exceeding 32, pointer manipulations, etc.

Conclusion

  • Summary of Importance:

    • Mastering these assembly and architecture concepts is essential for deep understanding of modern computing systems. RISC-V stands out for its simplicity and elegance in learning compared to more complex architectures like x86, leading to a better practical understanding that informs programming efficiency and effectiveness.