1.1.1 a) units, registers and buses of the CPU

units

the arithmetic and logic unit (ALU):

• completes all arithmetic and logic functions

• arithmetic operations on fixed/floating point numbers:

  • ADD, SUBTRACT, MULTIPLY and DIVIDE

• bitwise shift operations

• boolean logic operations:

  • comparisons

  • AND, OR, NOT and XOR

• results are often stored in general-purpose registers (e.g ACC)

the control unit (CU):

• coordinates all activities of the CPU

• directs flow of data between CPU and other devices

• accepts next instruction and decodes it

• handles execution of instructions and storing the resulting data in main memory or registers

• sends memory read/write requests to RAM along the control bus

• sends command and control signals such as bus requests/grants, and interrupt requests

• makes extensive use of the status registers and clock

• communicates with all elements of the CPU

registers

registers are small memory cells that operate at a very high speed, they are used to temporarily store data.

the program counter (PC):

• holds the address of the next instruction to be executed

• this could be:

  • the next instruction in a sequence

  • an address to jump to, if the previous instruction was to branch (this would be copied from the CIR)

• at the start of every FDE cycle, the instruction in the PC is copied to the MAR

the memory data register (MDR):

• used to temporarily store data that is to be read from, or written to memory

the memory address register (MAR):

• holds the address of a memory location from which data or an instruction is to be fetched, or which data is to be written to

• sends this address to memory down the address bus

the accumulator (ACC):

• data and control information often stored here

• stores the results of operations performed in the ALU

the current instruction register (CIR):

• holds the current instruction being executed

• contents of MDR are copied to the CIR (if MDR contains an instruction)

• contains the opcode and operand(s) of the instruction

buses

buses are a set of parallel wires which connect two or more components inside the CPU.

the width of the bus is the number of parallel wires the bus has:

• the width of the bus is directly proportional to the number of bits that can be transferred simultaneously at any given time

• buses are typically 8, 16, 32 or 64 wires wide

data bus:

• transports data and instructions (in binary) between components, bi-directional

address bus:

• transmits memory addresses specifying where data is to be sent to/retrieved from

control bus:

• transmits control signals between internal/external components

• coordinates the use of the address and data buses

• provides status information between system components

control signals:

• bus request: shows that a device is requesting the use of the data bus

• bus grant: shows that the CPU has granted access to the data bus

• memory write: data is written into the addressed location using this bus

• memory read: data is read from a specific location to be placed onto the data bus,

• interrupt request: shows that a device is requesting access to the CPU

• clock: used to synchronise operations

1.1.1 b) the Fetch-Decode-Execute cycle

fetch:

• the address of the next instruction is copied from the PC to the MAR

• contents of the MAR are sent along the address bus to memory, where it waits to receive a signal from the control bus

• the instruction held in the corresponding address is copied to the MDR by the data bus

• if the MDR holds an address, its contents are copied to the CIR

• the PC is incremented by 1

decode:

• the instruction in the CIR is split into opcode and operand

• the instruction is decoded in the decode unit

execute:

• the instruction is executed

• this may involve performing arithmetic operations in the ALU or storing the contents of the accumulator in a memory address in RAM

1.1.1 c) factors affecting CPU performance

clock-speed

• clock speed is determined by the system clock (an electronic device which generates signals, switching between 0 and 1)

• all processor activities begin on a clock pulse, and each CPU operation starts as the clock changes from 0 to 1

• clock speed is the time taken for one clock cycle to complete

• measured in GigaHertz (GHz)

• 1GHz = 1 billion instructions fetched per second

cores

• a core is an independent processor that is able to run its own FDE cycle.

• a computer with multiple cores can complete multiple FDE cycles at any given time

• a computer with dual cores can theoretically complete tasks twice as fast as a computer with a single core, however..

  • not all programs are able to utilise multiple cores efficiently as they have not been designed to do so

  • inter-core communication also requires processor time

cache memory

• cache memory is located on or near the CPU

• much faster to access than RAM

• instructions fetched from main memory are copied to the cache, so if required again, they can be accessed quicker

• as cache fills up, unused instructions are replaced

1.1.1 d) pipelining

pipelining is the process of completing the FDE cycles of separate instructions simultaneously, and holding appropriate data in a buffer in close proximity to the CPU until it’s required.

• it aims to reduce the amount of the CPU which is kept idle

• it is separated into instruction pipelining and arithmetic pipelining.

  • instruction: separating out the instruction into fetching, decoding, and executing

  • arithmetic: breaking down the arithmetic operations and overlapping them as they are performed

pipelining is inefficient when programs contain lots of branching, as each time a program branches, the processor will have to ‘flush the pipe’

1.1.1 e) processor architecture

harvard architecture

• instructions and data stored in separate memory units

• each has its own bus

• reading and writing data can be done at the same time as fetching an instruction

• used in RISC processors

von neumann architecture

• shared memory space for data and instructions

• built on the ‘stored program’ concept

• instructions and data stored in the same format

• a single control unit follows a linear FDE cycle

• one instruction at a time

contemporary processors use a combination, von neumann is used when working with data and instructions in main memory, but uses harvard architecture to divide the cache into instruction cache and data cache