COA Input Output Organisation
INPUT-OUTPUT ORGANIZATION
Asynchronous data transfer
Mode of Transfer
Priority Interrupt
Direct Memory Access
CPU Versus Peripherals
CPU
Electronic device
Fast data transfer rate
Data in the form of Words
Peripherals
Electromechanical or electromagnetic devices
Slow data transfer rate
Data in the form of codes
Input-Output Interface
Transfers information between internal storage (CPU & Memory) and external devices.
Synchronizes data flow between CPU and peripherals.
Input-Output Interface Communication
Typical communication link shows interaction between processor and peripherals.
Types of Commands for Interface
Control Command: Activates peripheral and instructs tasks.
Status Command: Tests status conditions in interface and peripheral.
Data Output Command: Transfers data from bus into a register.
Input Data Command: Receives data from peripheral and buffers it.
Example of I/O Interface
Includes:
Two data registers (ports)
Control register
Status register
Bus buffers
Timing and control circuits
Communicates with CPU via data bus.
Asynchronous Data Transfer
Internal operations synchronized by common clock pulses.
CPU and I/O Interface operate independently—often using their own clocks, resulting in asynchronous operation.
Modes of Asynchronous Data Transfer
Strobe Control
Source Initiated Strobe
Destination initiated Strobe
Handshaking
Source-initiated transfer.
Destination-initiated transfer.
Source-Initiated Strobe for Data Transfer
Data bus carries binary information from source to destination.
The strobe signals when data is valid on the bus.
Destination-Initiated Strobe for Data Transfer
Destination activates strobe, requesting data from the source.
Handshaking Overview
Resolves strobe method limitations by introducing a second control signal to confirm data transfer completion.
Ensures both units confirm data transfer participation.
Data Transfer Modes
Programmed I/O: CPU monitors peripheral for transfer readiness—time-intensive.
Interrupt Initiated I/O: CPU executes other tasks while waiting for an interrupt request from the interface.
Direct Memory Access (DMA): Allows devices to transfer data without constant CPU monitoring.
Priority Interrupt
Establishes priority among multiple requests to determine servicing order.
High-speed devices (e.g., disks) prioritized over slower devices (e.g., keyboards).