Digital Systems Design Fundamentals

Number Systems and Binary Codes

Digital technology processes analog quantities by converting them into digital formats using various number bases, including decimal (base 10), binary (base 2), octal (base 8), and hexadecimal (base 16). Positional values or weights determine the magnitude of digits, where the rightmost is the least significant digit ($LSD$) and the leftmost is the most significant digit ($MSD$). Binary systems use digits $0$ and $1$, octal uses $0$ to $7$, and hexadecimal uses $0$ to $9$ followed by letters $A$ through $F$. Conversion between these systems is accomplished through methods such as repeated division for decimal-to-binary/octal/hex transitions or grouping bits into three for octal and four for hexadecimal.

Several specialized codes facilitate data interaction and error reduction. The American Standard Code for Information Interchange ($ASCII$) represents characters using a $7$-bit standard ($128$ characters) or an $8$-bit extended version. Binary Coded Decimal ($BCD$) represents each decimal digit with a specific $4$-bit binary group. Gray code is a non-weighted code where only one bit changes between successive values, making it highly useful for mechanical switches and error correction in digital communications.

Fundamentals of Logic Gates

Logic gates are the fundamental building blocks of digital circuits, typically operating on positive logic where $0$ is FALSE and $1$ is TRUE. Input and output voltage ranges define these logic levels, separated by a transition region; the difference between these ranges provides a noise margin or guaranteed noise immunity. Actual pulse waveforms are characterized by rise and fall times, measured between $10\%$ and $90\%$ of the amplitude, and pulse width measured at $50\%$ amplitude.

Primary gates include AND (output HIGH only if all inputs are HIGH), OR (output HIGH if any input is HIGH), and NOT (inversion). NAND and NOR are classified as universal gates because any logic function can be implemented using them exclusively. Integrated circuits ($IC$), such as the $74LS00$ Quad NAND, house multiple gates in a single package using technologies like Transistor-Transistor Logic ($TTL$) or Complementary Metal-Oxide Semiconductor ($CMOS$).

Combinatorial Circuit Simplification

Combinatorial logic involves combining multiple gates to achieve specific outputs, which often requires simplification to reduce cost, size, and propagation delay. Boolean algebra provides the mathematical framework for this, utilizing commutative, associative, and distributive laws alongside fundamental axioms. DeMorgan’s Theorem is a critical tool for simplifying expressions with broad inversions, stating that $\overline{A \cdot B} = \bar{A} + \bar{B}$ and $\overline{A + B} = \bar{A} \cdot \bar{B}$.

Exclusive OR ($XOR$) and Exclusive NOR ($XNOR$) gates are specialized components where $XOR$ ($A \oplus B$) outputs HIGH only when inputs are dissimilar, and $XNOR$ outputs HIGH when they are the same. These gates are essential for parity checkers, which detect errors in data transmission by appending a parity bit to ensure the total count of $1$s is either even or odd.

Graphical Optimization with Karnaugh Maps

Logic expressions are typically represented in Sum of Products ($SOP$) or Product of Sums ($POS$) form. A more intuitive method for simplification than algebraic manipulation is the Karnaugh Map ($K$-map), which uses a grid following Gray code sequencing to group adjacent logic $1$s. These groups, or loops, must be as large as possible (powers of two: pairs, quads, octets) to eliminate the maximum number of variables. Don’t care conditions ($X$) represent input combinations that will never occur in a specific design, such as hex characters in a purely decimal seven-segment display, allowing for even larger loops and simpler resulting circuitry.

Sequential Logic and Multivibrator Circuits

Sequential circuits, or bistable multivibrators, possess memory by maintaining one of two stable states. Common flip-flops include $S-R$ (Set-Reset), $J-K$, $D$ (Data), and $T$ (Toggle). $J-K$ flip-flops, named after Jack Kilby, prevent the invalid state found in $S-R$ latches by toggling when both inputs are HIGH ($J=K=1$). Triggering is usually synchronized to a clock pulse via a Positive Going Transition ($PGT$) or Negative Going Transition ($NGT$). Flip-flops may also feature asynchronous inputs, such as PRESET ($\overline{PRE}$) and CLEAR ($\overline{CLR}$), which override the clock.

Other multivibrator types include monostable (one-shot), which produces a single pulse of duration $t_p$ when triggered, and astable, which acts as a free-running oscillator to generate clock signals. Using a $555$ timer IC, the frequency of an astable multivibrator is determined by external resistors and capacitors with durations $t_A = 0.693 \times R_2 \times C$ and $t_B = 0.693 \times (R_1 + R_2) \times C$, resulting in a frequency of $\frac{1}{t_A + t_B}$.

Arithmetic and Logic Design

Arithmetic operations in computers are performed by the Arithmetic Logic Unit ($ALU$). A half adder ($HA$) adds two bits to produce a sum $\Sigma_0 = A_0 \oplus B_0$ and a carry $C_1 = A_0 \cdot B_0$. A full adder ($FA$) expands this by including a carry-in ($C_0$) from previous stages. Multiple full adders can be cascaded to form parallel adders for multi-bit numbers, such as the $4$-bit $74LS283$ IC. Binary subtraction is typically implemented using addition via the $2$'s complement of the subtrahend, achieved by inverting bits ($1$'s complement) and adding $1$. Dual-mode circuits can switch between addition and subtraction using control inputs and $XOR$ gates.

Encoders, Decoders, and Multiplexers

Coders transform signal formats for digital processing. Encoders convert multiple input lines into a smaller number of binary output lines (e.g., $8$-to-$3$), with priority encoders like the $74xx148$ ensuring higher-indexed inputs take precedence during simultaneous activation. Decoders, such as the $74xx138$, perform the inverse, activating a specific output line based on binary input. Multiplexers ($MUX$) act as data selectors, routing one of several inputs to a single output based on select inputs. Conversely, de-multiplexers ($DEMUX$) act as data distributors, routing a single input to one of many possible outputs.

Counter Architecture and Design

Counters use flip-flops to cycle through a sequence of states. Asynchronous (ripple) counters trigger flip-flops sequentially, where the output of one serves as the clock for the next, which can lead to propagation delay errors. Synchronous counters trigger all flip-flops simultaneously with a common clock, ensuring higher reliability. Designing synchronous counters follows a structured process: creating a state diagram, choosing flip-flop types, deriving an excitation table (defining required inputs for state transitions), simplifying input expressions via $K$-maps, and drawing the final logic circuit.