Notes for L12 - CS305

Review of Logic Implementation in FPGAs

Field Programmable Gate Arrays (FPGAs) are critical for digital systems design, allowing flexibility in logic implementation. Each FPGA consists of Logic Elements (LEs) grouped to form Logic Array Blocks (LABs), which utilize faster local routing channels for efficient design execution.

Basic Structure of Logic Elements (LEs)

A typical LE consists of:

  • Look-Up Table (LUT): commonly a 4-input LUT, enabling various logical operations.

  • Flip-Flop: registers to store state information.

For enhanced functionality, such as arithmetic processing, additional components like 1-bit adders/subtractors can be integrated into the LE structure.
Furthermore, LEs can be expanded according to the unique requirements of the FPGA device in use.

Altera Quartus II Synthesis Process
Key Stages of Synthesis:

  1. Analysis & Synthesis: All design files are analyzed, and a unified database is created. During synthesis, the design logic is extracted and minimized.

  2. Fitter: Maps the synthesized logic onto the FPGA, determining the interconnection paths, pin assignments, and logic cells needed for the design.

  3. Timing Analysis: Computes the timing delays within the design to ensure that timing constraints, such as minimum clock frequency, are met.

  4. Simulation: Functional and timing simulations are crucial for verifying the correctness of design functionality. It helps in debugging the design model post-synthesis.

  5. Assembler: Converts the fitter's output into a programming image tailored for device configuration.

  6. Netlist Writer: Generates output netlist files compatible with other Electronic Design Automation (EDA) tools (e.g., VHDL output as .vho files).

Example of N-Bit Up/Down Counter
Functionality Overview:

The N-bit up/down counter integrates synchronous Enable and Reset inputs. Highlighted behavior includes:

  • When Enable is high (1), the counter actively counts.

  • If Reset is activated, the counter initializes either at 0 or at a maximum value (N-1) based on the UpDown signal. If UpDown is high (1), the counter increments; otherwise, it decrements.

Synthesis on Target Devices:

This counter can be synthesized for the following FPGA devices:

  • Cyclone IV E (EP4CE6E22C6)

  • Cyclone V (5CEBA4F23C7) or DE0-CV FPGA board.

VHDL Code Synthesis Analysis

The process of synthesizing VHDL code into LEs within the Cyclone IV FPGA can be exemplified through various coding structures:

Example Code Snippets:

  1. Example_R1: A simple logic operation.

   entity Example_R1 is   
       port (A, B : in bit_vector(15 downto 0);   
       C : out bit_vector(15 downto 0));   
   end entity Example_R1;   
   architecture a1 of Example_R1 is begin   
       C <= not (A xor B);  
   end architecture a1;

  • LE Calculation: Each LE can handle a 4-input LUT and a Flip-Flop. Therefore, it is important to evaluate the number of LEs based on high-level logic operations within the VHDL.

  1. Example_R2: Conditional logic for output generation.

   entity Example_R2 is   
       port (A, B : in bit_vector(15 downto 0);   
       D : in bit;    
       C : out bit_vector(15 downto 0));   
   end entity Example_R2;   
   architecture a2 of Example_R2 is begin   
       C <= A or B when D = '1' else A and B;  
   end architecture a2;

  • This example illustrates how branches in logic necessitate careful planning for LE count and resource allocation during synthesis.

Process Constructs in VHDL

The code examples presented also demonstrate processes, which are vital for state-driven designs. For example:

  1. Using a wait statement or edge-detection expressions infers Flip-Flops.

  2. An asynchronous reset mechanism where states are contingent on clock cycles and incoming signal inputs.

Reference Materials for Further Reading

  1. Logic and Computer Design Fundamentals by M. Mano and C.R. Kime

  2. Introductory VHDL from Simulation to Synthesis by Sudhakar Yalamanchili

  3. Fundamentals of Digital Logic with VHDL Design by Stephan Brown and Zvonko Vranesic

  4. The Designer’s Guide to VHDL by Peter J. Ashenden

  5. A VHDL Primer by J. Bhasker

These texts delve into advanced VHDL design methods, FPGA synthesis, and digital logic principles, thereby helping reinforce and expand the knowledge acquired in this course.