Chapter 0

INTRODUCTION TO COMPUTING

Chapter 0

1. NUMBERING AND CODING SYSTEMS


  • Decimal and Binary Number SystemsA. Decimal (base 10) and Binary (base 2) systems

    • Decimal: Uses digits 0-9 (e.g., 1, 56, 70, 2000)

    • Binary: Uses digits 0 and 1; represents two voltage levels (on/off).


  • Conversion between SystemsB. Converting from decimal to binary:

    1. Example: Convert 25 to binary:

      • 25/2 = 12 (R:1)

      • 12/2 = 6 (R:0)

      • 6/2 = 3 (R:0)

      • 3/2 = 1 (R:1)

      • 1/2 = 0 (R:1)

      • Therefore, 25 in binary is 11001.

    C. Converting from binary to decimal:

    1. Example: Convert 11001 to decimal:

      • 1x2^4 + 1x2^3 + 0x2^2 + 0x2^1 + 1x2^0 = 25.

    D. Hexadecimal System:

    • Base 16 representation of binary numbers (e.g., 10001001 = 89H).

    • Conversions:

      1. Binary to Hex: Group 4 bits at a time.

      2. Hex to Binary: Replace each hex digit with its 4-bit binary equivalent.


  • ASCII CodeH. Each character represented by binary patterns (7 bits, e.g., A = 01000001).

2. DIGITAL PRIMER


  • Binary LogicA. Computers use binary due to two voltage levels representing 0 and 1.


  • Logic GatesB. Types:

    1. AND Gate

    2. OR Gate

    3. Inverter

    4. XOR Gate

    5. NAND/NOR Gates


  • Logic Design Using GatesB. Components like Half-Adder, Full-Adder, and Flip-Flops.

3. SEMICONDUCTOR MEMORY


  • Types of MemoryA. Terminology:

    • KB = 1024 bytes, MB = 1024 KB, GB = 1024 MB, TB = 1024 GB.



  • Memory CharacteristicsB. RAM (volatile) vs ROM (non-volatile).C. Speed, organization, capacity, types of RAM (SRAM, DRAM) D. Examples of implementations (e.g., Memory chip organization).

4. BUS DESIGNING AND ADDRESS DECODING



  • Bus TypesA. Address bus, data bus, control bus.B. Role in CPU accessing memory and I/O devices.


  • Address DecodingC. Methods to decode addresses and activate selected memory chip.

5. I/O ADDRESS DECODING AND DESIGN


  • Output/Input Port DesignA. Using 74LS373 for output; 74LS244 for input.


  • Address DecodingB. Difference in Absolute vs Linear Select addressing, potential issues (e.g., aliases).

6. CPU ARCHITECTURE


  • Inside CPUA. Role and components of CPU: Program Counter, Instruction Register, ALU.


  • Architectural ModelsC. Difference between Harvard and von Neumann architectures:

    • Von Neumann: Same bus for code and data, slower.

    • Harvard: Separate buses for speed but requires more connections.


  • Execution OperationsB. Steps executed by CPU in processing instructions: fetching, decoding, executing.


INTRODUCTION TO COMPUTING

Chapter 0

1. NUMBERING AND CODING SYSTEMS

Decimal and Binary Number Systems

  • Decimal (Base 10): Utilizes digits 0 through 9. It is the numerical system that most people use daily, and expresses quantities such as 1, 56, 70, 2000, etc., encompassing both whole numbers and fractions.

  • Binary (Base 2): Consists solely of the digits 0 and 1, representing two distinct voltage levels: 0 for 'off' and 1 for 'on'. This system is foundational for computing as it aligns with the digital signals used in electronics.

Conversion between Systems

  • Decimal to Binary: The process involves repeatedly dividing the decimal number by 2, tracking remainders. For example, to convert 25 to binary:

    • 25/2 = 12 (R:1)

    • 12/2 = 6 (R:0)

    • 6/2 = 3 (R:0)

    • 3/2 = 1 (R:1)

    • 1/2 = 0 (R:1)

    • Therefore, in reverse, 25 in binary is 11001.

  • Binary to Decimal: This conversion takes each binary digit, multiplies it by 2 raised to its position power, and sums the results. For instance, for 11001:

    • 1×2^4 + 1×2^3 + 0×2^2 + 0×2^1 + 1×2^0 = 16 + 8 + 0 + 0 + 1 = 25.

  • Hexadecimal System: This base 16 system uses digits 0-9 and letters A-F (10-15). It serves as a more compact representation of binary data. For example, the binary number 10001001 translates to 89H in hexadecimal.

    • Conversions: To convert between binary and hexadecimal:

      • Binary to Hex: Group binary digits into sets of four.

      • Hex to Binary: Replace each hexadecimal digit with its corresponding 4-bit binary equivalent.

ASCII Code

  • The American Standard Code for Information Interchange (ASCII) is a character encoding standard that uses a 7-bit binary number for each character. For example, the uppercase letter 'A' is encoded as 01000001. This system is utilized in computers to represent text, allowing for consistent character representation across different systems and platforms.

2. DIGITAL PRIMER

Binary Logic

  • Binary logic is the foundation of modern computing. Computers use binary to process data because the binary digits (bits) align perfectly with the two voltage levels of electronic circuits, representing 0 and 1.

Logic Gates

  • Types of Logic Gates:

    • AND Gate: Outputs true only if all its inputs are true.

    • OR Gate: Outputs true if at least one of its inputs is true.

    • Inverter (NOT Gate): Outputs the opposite of the input; if the input is true, the output is false, and vice versa.

    • XOR Gate (Exclusive OR): Outputs true if the number of true inputs is odd; outputs false if even.

    • NAND Gate: Outputs true unless all inputs are true; the opposite of the AND gate.

    • NOR Gate: Outputs true only if all inputs are false; the opposite of the OR gate.

Logic Design Using Gates

  • Components: Logic gates can be combined to create larger circuits. Key components include Half-Adder, Full-Adder, and Flip-Flops, which are essential for performing arithmetic operations and storing data within digital systems.

3. SEMICONDUCTOR MEMORY

Types of Memory

  • Terminology:

    • 1 KB (Kilobyte) = 1024 bytes

    • 1 MB (Megabyte) = 1024 KB

    • 1 GB (Gigabyte) = 1024 MB

    • 1 TB (Terabyte) = 1024 GB

Memory Characteristics

  • Types of Memory:

    • RAM (Random Access Memory): A type of volatile memory that gets erased when power is lost. It is fast and used as temporary storage for data that the CPU needs in real-time.

    • ROM (Read-Only Memory): A non-volatile memory that retains its content even when the power is turned off; typically used to store firmware and system boot processes.

  • Speed and Organization:

    • Memory speed can vary; SRAM (Static RAM) is faster and used for cache memory, while DRAM (Dynamic RAM) is slower but more common in regular memory chips.

    • Various memory architectures include DIMM and SIMM, which dictate how memory is organized and accessed by the CPU.

4. BUS DESIGNING AND ADDRESS DECODING

Bus Types

  • Bus Architecture:

    • Address Bus: Responsible for carrying the memory addresses from the CPU to the relevant components. It is unidirectional, meaning it only carries data from the CPU outward.

    • Data Bus: This bidirectional bus transmits actual data between the CPU, memory, and I/O devices, facilitating communication.

    • Control Bus: Transmits control signals from the CPU to various components to coordinate operations and manage the flow of data.

Address Decoding

  • Techniques: Different methods are used to decode addresses, which is crucial to activate the appropriate memory chip at particular times, ensuring that the correct data is read or written.

5. I/O ADDRESS DECODING AND DESIGN

Output/Input Port Design

  • Components Used: Commonly used components include the 74LS373, which serves output functions, and the 74LS244, which handles input functions. These components help establish communication pathways between CPU and peripheral devices, such as keyboards and printers.

Address Decoding

  • Absolute vs Linear Select Addressing:

    • Absolute addressing refers to a direct selection of memory locations, while linear addressing utilizes a mathematical approach to define locations. Understanding these differences is vital to avoid issues like address aliasing, where multiple addresses might refer to the same physical memory.

6. CPU ARCHITECTURE

Inside CPU

  • Key Components:

    • The CPU comprises essential elements such as the Program Counter (PC), which tracks the addresses of the next instruction, the Instruction Register (IR), which holds the current instruction being processed, and the Arithmetic Logic Unit (ALU), responsible for executing arithmetic and logical operations necessary for computation.

Architectural Models

  • Harvard vs. Von Neumann Architectures:

    • Von Neumann Architecture: Shares the same bus for both data and instructions, which can limit speed due to a bottleneck.

    • Harvard Architecture: Employs separate buses for instructions and data, improving processing speed but requiring more complex circuitry.

Execution Operations

  • Processing Steps: The CPU performs a sequence of steps to execute instructions:

    • Fetching: The CPU retrieves the next instruction from memory into the Instruction Register.

    • Decoding: The CPU interprets the instruction to determine the required action.

    • Executing: The CPU performs the necessary action based on the decoded instruction, returning results or output as needed.