Introduction to Computer Science & Basic Programming Lecture Notes

Course Logistics, Grading, and Administrative Policies

  • Final Exam Logistics & WISER Platform

    • Final exam schedule details (date, time, and specific location) are published via the WISER platform.

    • The exact deadline and location are typically published approximately one to two weeks following the term setup.

    • Students must regularly check WISER to stay updated on official final examination details.

    • The remainder of the term consists of 1717 class sessions.

  • Attendance Grade Calculation Formula

    • Attendance accounts for 10%10\% of the total final course grade.

    • The attendance score is calculated proportionally based on total attended sessions out of the 1717 remaining sessions.

    • Calculation Formula:         Attendance Percentage=(Attended Sessions17)×100\text{Attendance Percentage} = \left( \frac{\text{Attended Sessions}}{17} \right) \times 100

    • Example: If a student misses 22 sessions out of 1717, they retain 1515 attended sessions:         Attendance Percentage=(1517)×100=88.24%\text{Attendance Percentage} = \left( \frac{15}{17} \right) \times 100 = 88.24\%

    • Exceeding 33 missed sessions does not lead to an automatic loss of the entire attendance grade; credit is awarded strictly on a proportional basis.

  • Course Grading Scale

    • 93.0%−100%93.0\% - 100\%: A

    • 90.0%−92.9%90.0\% - 92.9\%: A-

    • <60.0%< 60.0\%: F (Failure)

  • Homework Submissions and Autograder Mechanics

    • Programming assignments are compiled and evaluated automatically using an Autograder system against predefined test cases.

    • Test cases consist of both visible test cases and hidden test cases.

    • Submission errors or missing points indicate underlying syntax errors, semantic errors, or logic/runtime failures in the submitted code.

    • Students may submit assignments infinitely prior to the deadline; the Autograder evaluates and records only the final submission.

    • Manual Review: Teaching Assistants (TAs) manually review code to verify code comments, code structure, and the completed note file provided within assignment downloads.

    • Platform Requirement: Submissions must NOT be uploaded directly to Canvas. Students must access Gradescope via the hyperlinked Canvas assignment interface and drag-and-drop their .py files.

  • Late Submission Policy

    • Standard Deadline: Due dates are enforced at 11:59 PM11:59\,\text{PM}.

    • Grace Period & Late Penalties:

      • Up to 24 hours24\,\text{hours} late (≤1 day\le 1\,\text{day} late): 20%20\% deduction from the earned score.

        • Example: A homework grade of 9090 submitted 20 hours20\,\text{hours} late yields a final recorded score of 7070 (90−20=7090 - 20 = 70).

      • Between 24 hours24\,\text{hours} and 48 hours48\,\text{hours} late (>1 day> 1\,\text{day} and ≤2 days\le 2\,\text{days} late): 40%40\% deduction from the earned score.

      • Greater than 48 hours48\,\text{hours} late (>2 days> 2\,\text{days} late): Submissions are strictly blocked by Gradescope; no credit is permitted.

  • Academic Accommodations

    • Students requiring accommodations for quizzes or examinations must coordinate in advance with both the course instructor and the Ross Center to adjust exam dates and times.

  • iClicker Attendance Policy and Academic Misconduct

    • Attendance tracking utilizes iClicker via mobile phones, laptops, or tablets.

    • Procedure: The instructor opens an active iClicker session during class. Students check in electronically, followed by a direct roll-call verification at the end of the class session.

    • Misconduct Rules: Registering attendance via iClicker without physical presence in the classroom (e.g., checking in remotely from another location such as the McCormick building, or checking in and leaving early without permission) constitutes severe academic misconduct.

    • Penalty: Any remote or fraudulent check-in results in an immediate course attendance grade of 0%0\%.

    • Liability Rationale: The instructor holds legal responsibility for student safety during class hours while students are marked present in the system.

    • Early Departure Slip Procedure: If a student must leave class early, they must submit a physical slip to the instructor prior to departing containing:

      1. First Name and Last Name

      2. Current Date

      3. Exact Time of Departure

      4. Reason for Early Departure

      5. Student Signature

  • Artificial Intelligence (AI) Policy

    • Use of AI-generated text or coding assistance tools (such as AI autocompletion plugins in Visual Studio Code or conversational LLM text generators) is strictly prohibited on homework assignments.

    • Rationale: As a fundamental introductory programming course, students must independently master syntax, semantics, and underlying execution logic.

    • Oral Code Verification: Students may be randomly selected during office hours or after class to orally explain their submitted code line-by-line.

    • AI Violation Penalty: Receiving or utilizing AI assistance results in a grade of 00 or an immediate failure for the assignment.

    • Exam Cheating Penalty: Cheating on a midterm or final exam results in an immediate grade of 00 on the exam, a final grade of 0%0\% (F) for the entire course, and formal referral to the Academic Misconduct Office.

  • Key Examination Dates and Communication Rules

    • Midterm Examination: October 29, from 05:30 PM05:30\,\text{PM} to 06:45 PM06:45\,\text{PM} (Location assigned on Canvas).

    • Final Examination: Comprehensive written exam covering all material from the first session to the last; scheduled during the official examination window from December 14, 2026 to December 18, 2026.

    • Official Communication: Course updates are posted synchronously on Canvas and Discord.

    • Discord Conduct: Discussion of concepts is permitted, but students are strictly forbidden from sharing code or providing direct answers to peers.

Instructor Background and Research

  • Academic Background

    • Instructor Name: Sohail.

    • Education: Ph.D. in Computer Science from Michigan Technological University.

    • Ph.D. Dissertation Focus: Virtual Reality (VR) and Human Perception, specifically analyzing human distance perception in virtual environments.

  • History and Technical Challenges of Virtual Reality (VR)

    • Early VR hardware originated in the early 1970s, though significantly different from modern systems.

    • During the 1990s and early 2000s, VR hardware costs ranged from $30,000\$30,000 to $100,000\$100,000, preventing consumer accessibility.

    • In 2010–2011, Oculus commercialized consumer-grade VR hardware at approximate price points of $1,000\$1,000.

    • Distance Perception Inconsistency:

      • In physical reality, human visual estimation of distance (e.g., walking eyes-closed toward a target object on the floor) exhibits ≥95%\ge 95\% accuracy.

      • In virtual reality environments, human distance estimation accuracy drops to 70%−80%70\% - 80\%, producing an error rate of 20%−30%20\% - 30\%.

      • This 20%−30%20\% - 30\% error rate leads to critical failures in real estate visualization, surgical/medical simulations, architectural rendering, and military tactical training.

  • Active Computer Science Research Projects

    • 1. VR-Based Robotic Simulation and Gaze Tracking:

      • Utilizes NVIDIA Isaac (a GPU-accelerated robotic simulation engine) integrated with VR hardware.

      • Controls robotic mechanics through real-time eye-gaze tracking and collision detection with virtual target objects to annotate datasets for machine learning models.

    • 2. Unity Bifocal Rendering System:

      • Biological Mechanism: Real-world human eyes feature natural bifocal viewing. Focus on a near object (e.g., a finger) blurs the background; focus on a distant wall blurs the near object.

      • VR Hardware Limitation: Standard VR displays render images at fixed focal planes (typically 2.3 m−2.5 m2.3\,\text{m} - 2.5\,\text{m}) without physical focal depth variance, causing visual fatigue and spatial misjudgment.

      • Engineering Solution: Dynamic dynamic foveated blurring system using eye-trackers. Preserves full image clarity at the target gaze focal area (fovea) while applying variable threshold blurring to the peripheral visual field to mimic natural visual cues.

    • 3. Large Language Model (LLM) Terminal Integration ("Intuition"):

      • A project designed to eliminate rigid syntax constraints in command-line terminals.

      • Analogy: Non-native English speakers or immigrants may mispronounce or misspell words, yet human listeners comprehend the underlying intent. LLM systems are integrated into terminal layers to act as fuzzy interpreters, translating misspelled syntax into correct computational execution.

Information Representation, Binary Systems, and Computer Architecture

  • Decimal vs. Binary Systems

    • Decimal System (Base-10):

      • Uses 1010 unique numeric digits: {0,1,2,3,4,5,6,7,8,9}\left\{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 \right\}.

      • Standard format used in daily human activity (tuition payments, wages, time measurement).

    • Binary System (Base-2):

      • Uses 22 unique numeric digits: {0,1}\left\{ 0, 1 \right\}.

  • Hardware Rationale for Binary Representation

    • Physical Implementation: Computers rely on electronic circuits, transistors, and switches operating under voltage thresholds.

    • Voltage Ranges & Noise Immunity:

      • Logic 00: Represented by low voltage ranges (e.g., 0 V−0.5 V0\,\text{V} - 0.5\,\text{V} up to 4 V4\,\text{V}).

      • Logic 11: Represented by higher voltage ranges (e.g., 4 V−12 V4\,\text{V} - 12\,\text{V}).

      • If engineers attempted to map 1010 distinct decimal digits to 1010 narrow voltage bands, electrical noise, heat, and voltage fluctuations would cause constant calculation corruption.

      • Binary systems isolate states into two broad voltage bands, creating high noise immunity and hardware stability.

    • Computational Trade-Off: Binary hardware design simplifies physical circuit logic, but increases algorithmic complexity for basic operations (addition, subtraction, multiplication, division), requiring Boolean algebra and digital logic gates.

  • Binary Numerical Mechanics and Conversions

    • Unsigned Range Formula: For an nn-bit unsigned binary sequence, the maximum range of unique integers represented is:         Range=0 to 2n−1\text{Range} = 0 \text{ to } 2^n - 1

    • Unsigned Binary Counting Sequence:

      • 010=020_{10} = 0_2

      • 110=121_{10} = 1_2

      • 210=1022_{10} = 10_2 (Addition of 12+121_2 + 1_2 causes least significant bit overflow: 00 with a carry of 11)

      • 310=1123_{10} = 11_2

      • 410=10024_{10} = 100_2

      • 810=100028_{10} = 1000_2

      • 910=100129_{10} = 1001_2

      • 1010=1010210_{10} = 1010_2

    • Signed Representation: Binary numbers are inherently unsigned. Negative values require mathematical conventions such as Two's Complement.

  • Evolution of Computer Architecture

    • Early Hardware (1950s–1960s):

      • Early computers occupied entire rooms or buildings.

      • Calculations relied on large, fragile vacuum tubes to execute arithmetic logic.

    • Von Neumann Architecture:

      • Proposed by John von Neumann in the mid-20th century.

      • Defines the structural blueprint for modern electronic computing devices (laptops, phones, tablets).

      • Core Functional Units:

        1. Arithmetic Logic Unit (ALU): Executes mathematical computations and Boolean logic operations.

        2. Input/Output Systems (I/O): Interfaces with external peripheral inputs and user outputs.

        3. Storage / Memory Unit: Stores instructions and active data sets.

        4. System Bus: High-speed communication channels connecting ALU, I/O, and Storage.

    • Transistor Revolution and Modern Integration:

      • Invention of the solid-state transistor (pioneered by William Shockley and colleagues) replaced bulky vacuum tubes.

      • Modern Central Processing Units (CPUs) contain tens to hundreds of billions of integrated transistors manufactured via high-precision holographic photolithography systems (such as those developed by ASML).

      • Transistor networks execute fundamental digital logic gates (AND\text{AND}, OR\text{OR}, XOR\text{XOR}, NOT\text{NOT}), forming the hardware foundation for complex processing, personal computing, and space exploration achievements such as the Moon landings.