Machine Structure II: Sequential Logic Circuits Study Guide

Introduction to Sequential Logic Systems

• Definition: Sequential logic systems are foundational components of digital electronic circuits. They are defined as combinational logic systems integrated with memory elements. This integration allows the circuit to store and recall information regarding past inputs.

• Functional Dependencies: The outputs of a sequential circuit depend on two factors:

  • The present state of the inputs.

  • The values of bits stored in the memory unit (past history).

• Memory Elements: Flip-flops serve as memory elements that store binary information in the present. They interact with combinational circuits to modify and save information, thereby determining the next state of the circuit. This mechanism allows circuits to react to new data while maintaining a record of previous events.

• Circuit Objectives:

  • Understanding the differentiation between combinational and sequential circuits.

  • Differentiating between synchronous and asynchronous circuits (Latches and Flip-flops: RS, T, D, and JK).

  • Analyzing sequential logic through state tables, state equations, and state diagrams.

  • Designing synchronous sequential circuits using Flip-flops and logic gates.

  • Analyzing and designing Registers and Counters.

Classifications of Sequential Logic

Sequential logic is categorized based on timing and synchronization into two primary types:

• Synchronous Sequential Logic:

  • Synchronization: The operation is governed by a global clock signal.

  • Triggering: The circuit responds to input changes or triggers events only at specific instants defined by the clock pulses.

  • Advantages: These circuits are generally easier to design and analyze because the predictable timing simplifies the synchronization of various components.

• Asynchronous Sequential Logic:

  • Synchronization: Does not rely on a global clock signal.

  • Triggering: The circuit responds to input changes or events immediately as they occur.

  • Advantages: Potentially more responsive and possess a simpler structure due to the absence of a global clock.

  • Disadvantages: More challenging to design and analyze because of the lack of a centralized timing mechanism.

Clock Signals and Triggering

• Clock Signal: A periodic electrical signal serving as a timing reference. It oscillates between two voltage levels (High and Low) in a repeating pattern.

• Key Characteristics:

  • Period $(T)$: The time required for one complete cycle (e.g., from one rising edge to the next rising edge).

  • Frequency $(f)$: The number of clock cycles per second, measured in Hertz $(Hz)$. It determines the rate of operations: $f = \frac{1}{T}$.

• Reference Points: The transition points are used as references for triggering events:

  • Rising Edge ($\Delta$): Transition from Low to High.

  • Falling Edge ($\nabla$): Transition from High to Low.

• Types of Triggering:

  • Edge Triggering: Actions occur specifically during transitions (Rising or Falling). This is common in synchronous systems.

  • Level Triggering: Actions occur while the signal is at a specific level (High Level or Low Level). Often found in asynchronous systems.

• Edge Detection Circuitry: Edge triggering detection is achieved by feeding the clock signal into an AND gate, where one input is direct and the other is inverted through a NOT gate. The delay introduced by the NOT gate (several nanoseconds) causes a slight shift between the signals, making the AND gate produce a pulse at the transition.

Latches and Flip-Flops

• General Definition: Digital logic elements used to store one bit of binary data. An element capable of storing data is referred to as a memory.

• Latches vs. Flip-Flops:

  • Latches: Function based on signal levels (level-sensitive).

  • Flip-Flops: Conditioned by clock transitions (edge-sensitive).

Asynchronous Latch Circuits

• Basic Memory Latch: A simple feedback loop where if the Latch Command is forced High $(1)$, the output $Q$ becomes HI and remains HI via the feedback loop even if the command returns to Low $(0)$. The only way to "unlatch" such a circuit is to remove the power supply.

• RS Latch (NOR Gate implementation):

  • Contains two NOR gates with two inputs ($R$ and $S$) and two outputs ($Q$ and $Q'$).

  • Set (S): Forces $Q = 1$.

  • Reset (R): Forces $Q = 0$.

  • Memorization: When $S = 0$ and $R = 0$, the output remains in its previous state.

  • Forbidden State: $S = 1$ and $R = 1$ is forbidden as it creates an invalid output state.

• RS Latch (NAND Gate implementation):

  • Uses Low-level inputs to activate signals.

  • Set (S): Activated by Low level $(0)$, forces $Q = 1$.

  • Reset (R): Activated by Low level $(0)$, forces $Q = 0$.

  • Memorization: Occurs when both inputs are High $(1)$.

  • Forbidden State: Both inputs strictly at Low $(0)$.

• Gated RS Latch:

  • Adds an Enable ($En$) input. Inputs $S$ and $R$ only control the state when $En$ is High.

• Gated D Latch:

  • Has one data input ($D$) and an enable ($En$).

  • The $D$ input is connected to the $S$ input directly and the $R$ input via a NOT gate.

  • When $En = 1$, the output $Q$ follows $D$ ($Q = D$).

Synchronous Flip-Flops

Synchronous flip-flops change states only at specific points relative to the clock signal. Symbols define sensitivity:

• Empty circle/None: High-level sensitivity.

• Bubble: Low-level sensitivity.

• Triangle: Rising-edge sensitivity.

• Triangle + Bubble: Falling-edge sensitivity.

Common Types and Characteristics

• D Flip-Flop:

  • Single input $D$. $Q$ follows $D$ at the triggering edge.

  • Characteristic Equation: $Q_{n+1} = D$.

• JK Flip-Flop:

  • Inputs $J$ (Set), $K$ (Reset/Clear).

  • When $J=1, K=0 \rightarrow Q=1$.

  • When $J=0, K=1 \rightarrow Q=0$.

  • When $J=0, K=0 \rightarrow \text{Hold state}$.

  • When $J=1, K=1 \rightarrow \text{Toggle state}$ (state alternates).

  • Characteristic Equation: $Q_{n+1} = J A_n + \bar{K} A_n$.

• T Flip-Flop (Toggle):

  • Single input $T$. If $T=1$, output toggles at clock pulse. If $T=0$, it holds state.

  • Can be made from a JK flip-flop by tying $J$ and $K$ inputs together.

  • Characteristic Equation: $Q_{n+1} = T \bar{Q}_n + \bar{T} Q_n$.

• RS Flip-Flop:

  • Standard Set/Reset behavior synchronized by clock.

  • Forbidden state when both inputs are High.

Asynchronous Preset and Clear Inputs

• Preset (PRE): When activated (usually active-Low), forces $Q = 1$ immediately, independent of the clock or synchronous inputs.

• Clear (CLR): When activated (usually active-Low), forces $Q = 0$ immediately, independent of the clock or synchronous inputs.

• Operation: When both are disabled (High), the flip-flop operates synchronously based on its data inputs and clock.

Sequential Circuit Analysis

Analysis involves determining the functional behavior of a circuit from its diagram, resulting in state equations, tables, or diagrams.

• Finite State Machines (FSM):

  • Moore Machine: Outputs are associated specifically with states. Changes occur synchronously with state transitions.

  • Mealy Machine: Outputs are associated with state transitions. Changes depend on both the current state and the inputs.

• Analysis Procedure:

  1. Step 1: Write the Flip-Flop (FF) input equations (e.g., $D_A$, $D_B$) in terms of present states ($A_n$, $B_n$) and external inputs ($X$).

  2. Step 2: Write the state equations. Determine future states ($A_{n+1}$, $B_{n+1}$) by substituting input equations into the FF characteristic equations.

  3. Step 3: Elaborate the State Table. This table includes present states, external inputs, future states, and external outputs.

  4. Step 4: Draw the State Diagram. Use circles for states and arrows for transitions (labeled In/Out for Mealy machines).

Sequential Circuit Design (Synthesis)

Design involves creating a logic circuit from a functional description.

• Synthesis Steps:

  1. Derive a state diagram from specifications.

  2. Perform State Reduction if necessary (eliminate redundant states).

  3. Assign binary values to states (Pure binary, Gray code, or One-hot).

  4. Obtain the binary-coded state table.

  5. Select Flip-Flop types ($D$, $JK$, etc.) and add Excitation Tables.

  6. Derive simplified FF input and output equations using K-maps.

  7. Draw the logic diagram.

• Excitation Tables: Define what inputs are needed to achieve a specific transition from $Q_n$ to $Q_{n+1}$:

  • D-FF: $D = Q_{n+1}$.

  • T-FF: $T = 0$ for no change, $T = 1$ for change.

  • JK-FF:

    • $0 \rightarrow 0$: $J=0, K=X$

    • $0 \rightarrow 1$: $J=1, K=X$

    • $1 \rightarrow 0$: $J=X, K=1$

    • $1 \rightarrow 1$: $J=X, K=0$

• State Reduction: Process of identifying equivalent states. Two states are equivalent if for the same input, they transition to equivalent next states and yield identical outputs. Redundant states are removed and references are updated.

Registers

• Definition: Digital circuits designed for storing and transferring binary data. They consist of a cascaded arrangement of flip-flops (usually D-type).

• Applications: Memory addressing, data storage in microprocessors, I/O operations, and arithmetic/logic operations.

• Operational Modes:

  • SISO (Serial-In Serial-Out): Data enters bit-by-bit and exits bit-by-bit. Shifts one position per clock pulse.

  • SIPO (Serial-In Parallel-Out): Data enters bit-by-bit; all stored bits are available simultaneously as outputs.

  • PISO (Parallel-In Serial-Out): Data enters all at once via a Shift/Load control and exits bit-by-bit.

  • PIPO (Parallel-In Parallel-Out): Data enters and exits all at once in a single clock cycle.

  • Shift Operations: Right Shift, Left Shift, Rotate Right, and Rotate Left.

• Bidirectional/Universal Registers: Can shift data in more than one direction or perform both serial/parallel operations depending on control signals.

Counters

• Definition: Digital circuits used to count pulses or events, outputting a binary number representing the count.

• Modulus (MOD-number): The number of unique states a counter cycles through before returning to zero. A counter with $N$ flip-flops has a maximum modulus of $2^N$.

• Synchronous Counters: All flip-flops are triggered by the same global clock signal simultaneously. Logic determines state transitions.

• Asynchronous (Ripple) Counters:

  • The clock is applied only to the first flip-flop (LSB).

  • Subsequent flip-flops are clocked by the output of the preceding stage.

  • All flip-flops operate in Toggle mode.

  • Triggering Rules for Count Direction:

    • Falling edge trigger + connection to $Q$ = Up Counter.

    • Falling edge trigger + connection to $Q'$ = Down Counter.

    • Rising edge trigger + connection to $Q'$ = Up Counter.

    • Rising edge trigger + connection to $Q$ = Down Counter.

• Variable Modulus Counters: Examples include BCD (Binary Coded Decimal) counters, which count from 0 to 9 ($MOD-10$). To create larger counters (e.g., up to 1000), multiple BCD counters are cascaded, with detection logic (e.g., AND gates detecting '1001') used to trigger the next decade digit.

Questions & Discussion

• Analyze the function of a specific circuit: Analysis might reveal behavior such as alternating between two stable states or ignoring certain transitions depending on input $X$.

• Design Exercise: Designs can be implemented using different flip-flop types (e.g., design a MOD-4 counter using JK-FFs vs D-FFs).

• State Assignment: Use methods like One-hot assignment for specific design scenarios discussed in exercise prompts.