Logique Programmable (FPGA @VHDL)

Logique Programmable (FPGA @VHDL)

Introduction

• The digital world relies heavily on informatics, telecommunications, and automotive systems.

• Informatics includes microprocessors, graphic processors, audio processors, internet, games, office automation and scientific calculation.

• Telecommunications utilizes low power microcontrollers, sound processing, image transmission, internet, UMTS (video transmission), and software radio.

• Automotive systems feature multiple microprocessors for active and passive safety, engine performance, comfort, and multimedia.

• Increasingly present in everyday life (computers, PDA's, GSM, GPRS, UMTS, GPS, digital TV, embedded automobile electronics, CD/MP3/DVD players, signal processing).

• Explosion of needs: doubling the number of intelligent objects and embedded complexity.

• Each industry faces specific constraints.

Evolution of Mobile Communication

• 1G (1981): Analog voice/SMS service.

• 2G (1992): Digital voice/SMS service (GSM).

• 3G (2001): Digital data/PS (384K).

• 3.5G (2004): Data/PS (42M).

• 3.9G (2007): Data/PS (300M).

• 4G (2011): App/SNS service, LTE (1Gps).

• 5G (2020): Cloud/Big Data service, 100X 4G, VRI Service + IoT (10Gps, expect).

  • Key Milestones and Technologies:

    • 3GPP R99 (2001).

    • Rebase 6 (2004).

    • Rebase 7 (2006).

    • LTE, R8.

    • LTE-A, R10.

    • RIT, R15/R16.

  • Standards and Recommendations:

    • ITU-R M.1457 (2001).

    • BIT Adarted Recomendation (2012).

    • ITU-RM 2012 MT.R:SPEC].

    • LTE-Advanced.

    • ITU-R IMT.2020 MT-2000 Recommen.

Motivations for Programmable Logic

• Reduce prototyping time --> time-to-market.

• Reduce production costs.

• Low power consumption.

• Small system size.

• Reliability.

• The specifications for developing a system must take these parameters into account.

Alternatives

• ASIC (Application Specific Integrated Circuits).

• Programmable logic devices.

Levels of Implementation

• Circuit: Transistors (Vin, Vout).

• Device: n+S, D, n+G.

• Gate.

• Module.

• System: Précision, Accélération.

Logic Integrated Circuits

• Specialized ICs are used to implement logic functions.

• Two main families of logic ICs:

  • TTL (Transistor Transistor Logic):

    • Made with bipolar transistors.

    • Supply voltage: $V_{cc} = (5 \pm 0.25)V$

    • Input:

      • 0 to 0.8V: Logic level 0.

      • 2 to 5V: Logic level 1.

    • Output:

      • 0 to 0.4V: Logic level 0.

      • 2.4 to 5V: Logic level 1.

• Example: 7400 integrated circuit

  • Features four NAND logic functions (or gates) with 2 inputs each.

  • Pinout and internal schematic of a NAND gate are provided.

  • Internal resistances of the NAND gate are shown (4 kΩ, 1.8 kΩ, 130 Ω, 1 kΩ).

  • The supply voltage $V_{cc}$ is +5V.

  • The output s=ab corresponds to a NAND function.
    Figure 2: Pinout
    Figure 3: Internal Diagram of a NAND port

CMOS Logic

• CMOS (Complementary Metal Oxide Semiconductor):

  • Made with MOSFET transistors.

  • Supply voltage: 3 to 18V.

• Example: integrated circuit 4069B

  • Contains six NOT inverter gates.

  • $s = \overline{e}$

  • VDD (Supply Voltage)

  • Vss (Ground)

• Note: CMOS and TTL families are not compatible.
  Figure 4 and 5

Transistor Technologies

• CMOS (Complementary Metal Oxide Silicon):

  • High integration density.

  • Low power.

• Bipolar:

  • Higher frequency than CMOS.

  • High output current.

  • More power consumption.

• BiCMOS:

  • Combining CMOS and Bipolar technologies.

• SOI (Silicon On Insulator):

  • High integration density.

  • Very fast circuits.

  • Very low power.

  • Very expensive.

Traditional Prototyping

• Involves discrete components, breadboards, and manual wiring for creating logic circuits.

• Example circuit diagram shows interconnected logic gates (e.g., 4011, 4001) with resistors and power connections.

• Illustrates a hands-on approach to circuit design.

Programmable Logic Devices (PLD)

• A classic circuit contains logic gates, connections between the gates, memory elements (registers and/or memory), inputs/outputs, and clocks.

• A CLP (Configurable Logic Platform) must have the same functionalities with the notion of "programmability".

• Logical circuits, more or less complex, replace combining multiple logic boxes.

  • Simplified cabling.

  • Reduced footprint.

  • Reduced costs.

  • Ease of use.

  • Reduced risk of failures.

Families of Programmable Logic Circuits

• Two major families:

  • PROM (Programmable Read-Only Memory).

  • PLD (Programmable Logic Device).

Programmable Logic Devices

• PLD

• EPLD-CPLD

• FPGA

PLD Types

• PAL, GAL (Programmable Array Logic, Generic Array Logic).

• EPLD-CPLD (Erasable PLD or Complex PLD)

  • EPLDs are electrically programmable and UV erasable.

  • EEPLDs are electrically erasable.

  • Similar principle to PAL but with interconnections made using UVPROM technology.

• FPGA (Field Programmable Gate Array)

  • An array of elementary logic blocks that the user can interconnect to implement desired logic functions.

Basic Structure of a PLD

• GALs are PALs using CMOS technology, making them programmable and electrically erasable.

• They have programmable "AND" matrices and fixed "OR" matrices.

• This operation is performed using a suitable programmer.

• Large silicon area used.

• These circuits are no longer used today.

PLD Programming

• An example shows a PLD programmed to implement logic functions:

  • $Q0 = a \cdot b + \overline{a} \cdot \overline{b}$

  • $Q1 = a \cdot \overline{b} + \overline{a} \cdot b$
    Figure : Intact Fuse

Input/Output Configuration

• Some pins of these circuits can be used as either inputs or outputs using a 3-state logic system.

• The control of this 3-state logic is configured during programming.

• The output structure also allows for feedback of the outputs to the inputs.

CPLD (Complex Programmable Logic Device)

• Set of logic blocks LAB (Logic Array Block) composed of macrocells.

• A macrocell implements a combinational logic function + flip-flop.

• A Programmable Interconnect Array (PIA).

• Each I/O is linked to a macrocell.
  Figure: PAL hierarchical architecture (EPLD)

• CPLDs were the precursors to the first FPGAs.

• These circuits are no longer used today as they have been replaced by FPGAs.

FPGA (Field Programmable Gate Array)

• Advantages:

  • Technology is "easy" to master.

  • Reduced development time.

  • Reprogrammable.

  • Low cost.

• FPGAs consist of a matrix of programmable logic blocks surrounded by programmable input/output blocks.

• The whole is connected by a network of programmable interconnections.

• FPGAs are distinct from other families of programmable circuits, offering the highest level of logic integration.

Internal Architecture of an FPGA

• Key components: IOEs, LABs, M4K RAM Blocks, M512 RAM Blocks, DSP Blocks, M-RAM Block.

• IOEs support various I/O standards (DDR, PCI, GTL+, SSTL-3, SSTL-2, HSTL, LVDS, LVPECL, PCML, HyperTransport).

• LABs (Logic Array Blocks).

• RAM Blocks for memory functions (Dual-Port Memory, Shift Registers, FIFO Buffers).

• DSP Blocks for multiplication and FIR filters.

• Example: Stratix d'ALTERA.

Comparison of Programmable Logic Families

Hardware Description Languages (HDL)

• With a hardware description language and a programmable circuit such as an FPGA, a designer can quickly develop and simulate a sophisticated digital circuit, implement it on a prototyping board, and verify its operation.

• Instructions written in these languages translate into a logical configuration of gates and flip-flops that is integrated inside the programmable logic circuits.

  • VHDL is a standard and international language.

  • Allows the description in text form of a digital system:

    • For simulation of logic systems.

    • For implementation in a programmable digital circuit (CPLD, FPGA, etc.).

  • Language independent:

    • From the environment used (Quartus, Xilinx…).

    • From the final target (EPLD Altera, FPGA Xilinx, ASIC, etc.).

  • Blocks of instructions executed simultaneously.

  • Takes into account reality: possibility of specifying delays, specifying what happens in case of bus conflicts, etc.

VHDL and Synthesis Process

• VHDL code describes the behavior of the system, including combinational and sequential functions.

• Simulation software is used to verify the VHDL code.

• Synthesis software translates the VHDL code into a configuration for programmable logic circuits (e.g., Xilinx, Digilent).

• Target devices: Xilinx Spartan series.

VHDL Writing Rules

• No distinction between lowercase and uppercase letters.

• Comments: start with two hyphens and continue until the end of the line. Ignored by the compiler.

• In general, instructions end with ";".

• Naming rules: 26 letters of the alphabet, the 10 digits, and '_'.

• The first character must be a letter.

• There cannot be two "_" in a row.

Explicit Values in VHDL

• Integer: 123, 1_2_3

• Based Integer: base#value#

  • 2#11# (3)

  • 16#1F# (31)

• Physical Values: always leave a space between the value and the unit

  • 100 ps

  • 2 ns

  • 5 V

• Character: between apostrophes

  • 'a'

  • '@'

• Bit: between apostrophes

  • '0'

  • '1'

  • 'Z'

• String: between quotation marks (case-sensitive)

  • "Bonjour "

• Bus: between quotation marks

  • "01111001 "

• Boolean: true, false

Reserved Words in VHDL

Keywords:
abs, access, after, alias, all, and, architecture, array, assert, attribute, begin, block, body, buffer, bus, case, component, configuration, constant, disconnect, downto, else, elsif, end, entity, exit, file, for, function, generate, generic, group, guarded, if, in, inout, is, label, library, linkage, loop, map, mod, nand, new, next, nor, not, null, of, on, open, or, others, out, package, port, procedure, process, property, protected, range, record, register, reject, rem, report, return, rol, ror, select, severity, signal, sla, sll, sra, srl, subtype, then, to, transport, type, unaffected, units, until, use, variable, vmode, vprop, vsequence, wait, when, while, with, xnor, xor

Combinational Operations

• Study of a comparator of two 4-bit numbers.

• The comparator compares two numbers of four binary elements each.

• Constituent parts:

  • Inputs A and B of four bits each.

  • Output A = B.

• The body of the design delimits the boundary between the internal structure of the comparator and the external world.

Simple Organization of a VHDL Description

• A VHDL description consists of two parts: an entity and an architecture.

• The entity describes the interface between the design and the external world.

• The architecture describes the internal structure of the component. There are several ways to describe this operation.

VHDL Description of a Comparator

• The entity is described using the PORT instruction, which lists the different inputs and outputs of the design. For each data transferred through a PORT, its mode and type are defined.

-- comparator of two four bits
ENTITY eqcomp4 IS
    PORT (
        a0, a1, a2, a3 : IN BIT;
        b0, b1, b2, b3 : IN BIT;
        aeqb : OUT BIT
    );
END eqcomp4;

ARCHITECTURE logique OF eqcomp4 IS
BEGIN
    aeqb <= '1' WHEN ((a0=b0) and (a1=b1) and (a2=b2) and (a3=b3)) ELSE '0';
END logique;

VHDL Entity

• The input/output signals of the entity are PORTS.

• A PORT is defined by:

  • A name.

  • A mode (direction).

  • A type.

• The MODE corresponds to the direction of transfer:

  • IN: input (unidirectional).

  • OUT: output (unidirectional).

  • INOUT: input/output (bidirectional).

  • BUFFER: looped output.

• The IN mode protects the signal in writing.

• The OUT mode protects the signal in reading.

VHDL: Type

• The type can be a bit, bit_vector, std_logic, std_logic_vector, an integer, or a user-defined type. Some types require the use of a specific library to be used.

• Another type can be used by grouping the inputs into two vectors of four bits each.

VHDL: Types

• Every VHDL object must be associated with a type (object = signal, constant, or variable).

• A type defines:

  • The set of possible values.

  • The set of available operators.

• Organization of types in VHDL:

  • Predefined types (integer, bit, bit_vector, boolean, etc.).

  • Complementary types

    • IEEE1164 (std_logic, std_logic_vector).

    • Specific types defined by the tools of the suppliers.

    • User types (enumerated type, subtype).

VHDL: Type Categories

• Scalar types (numeric and enumerated).

• Composite types (arrays and vectors).

• Possibility to define new types.

• Scalar Types:

  • Enumerated types: list of values.

  • Numeric types: definition range (range to, downto).

• Composite Types: collections of elements of the same type identified by index values.

VHDL: Predefined Types and Operators

VHDL: Example

-- Let A and B be of type 3 bits and S1 of type 8 bits
-- A = "001" and B ="110"
S1 <= A & B & "01" ; -- S1 will take the following value after this assignment
-- S1 = "001110 01“
S1 <= A sll 2 ; -- S1 = A shifted by 2 bits to the left.
S2 <= A rol 3 ; -- S2 = A with a rotation of 3 bits to the left

VHDL: Shift Operations

• To perform logical shifts in logic synthesis, it is preferable to use the following instructions:

  • Right Shift: If A is of type std_logic_vector(7 downto 0)

S1 <= ‘0’ & A(7 downto 1); -- right shift of one bit
S1 <= "000" & A(7 downto 3); -- shift of three bits to the right

*   Left Shift: If A is of type std\_logic\_vector(7 downto 0)

S1 <= A(6 downto 0) & ‘0’; -- left shift of one bit
S1 <= A(4 downto 0) & "000"; -- shift of three bits to the left

VHDL: Arithmetic Operators

• To use these operators, add the following libraries to the beginning of the VHDL file:

Use ieee.numeric_std.all ;
Use ieee.std_logic_arith.all ;

• Examples:

S1 <= A – 3 ; -- S1 = A – 3
-- We subtract 3 from the value of the input/signal A
S1 <= S1 + 1 ; -- Increments signal S1 by 1

• Note: Using these operators with signals that have a large number of bits can generate large electronic structures.

• Examples:

S1 <= A * B ;-- S1 = A multiplied by B : A and B are coded on 4 bits
S2 <= A / B ;-- S2 = A divided by B : A and B are coded on 4 bits

VHDL: std_logic Type (IEEE1164)

• Allows defining the types, operators, and base conversion functions.

• The bit type of VHDL can take the values '0' and '1'. This type is insufficient to describe real logic signals (high impedance, forcing, etc.).

• The IEEE1164 standard defines multi-value signals that meet the needs of real systems and facilitate simulation.

• The type std_logic (and std_logic_vector) has 9 values:

  • '0', '1', 'X', 'L', 'H', 'W', 'Z', 'U', '-'

• The use of the std_logic type is possible via the IEEE1164 library

library ieee;
use ieee.std_logic_1164.all;

VHDL: Libraries.

• Any VHDL description used for synthesis needs libraries.

• The IEEE (Institute of Electrical and Electronics Engineers) has standardized them, especially the IEEE1164 library.

• They contain the definitions of electronic signal types, functions, and subprograms for performing arithmetic and logical operations.

VHDL: Library Declaration

• Declaring a Library is done at the beginning of a program.

library IEEE;
use ieee.std_logic_1164.all; -- definition of the bit type, bit vector, etc.
use ieee.std_logic_arith.all; -- signed or unsigned operations
use ieee.numeric_std.all; -- signed or unsigned operations

Do not use the libraries numeric_std and std_logic_arith at the same time: std_logic_arith is an improved version of numeric_std.

VHDL: User-Defined Types (Examples)

• Syntax for a type declaration:

type name_of_integer_type is range start to end;
type name_of_enumerated_type is (list of values);
type name_of_array_type is array (start to end) of element_type;

• Examples:

type memory_size is range 1 to 1024; -- ascending interval
type state is (reset, stop, wait, go);
type my_word is array (0 to 31) of bit;
type truth_table is array (bit, bit) of bit;

VHDL: Entities

• Object = named element having values of a given type

• 4 classes of objects:

  • Constants

  • Variables

  • Signals

  • Files

• Constant has a fixed value during simulation.

• Declaration of a constant:

constant constant_name : type [:= expression] ;

example:
constant PERIODE : time :=20 ns;
constant BUS : std_logic :=‘1’;

VHDL: Constants

• A constant must be declared before use.

• It can be declared:

  • In a package, it is then global.

  • In an entity, it is then common to all architectures of the entity.

  • In the architecture, it is then local.

• The assignment is done with the operator ":=".

VHDL: Variables

• Variables are objects used to store an intermediate result to facilitate the construction of a sequential algorithm. They can only be used in processes, procedures, or functions, and in "Generate" loops.

• Declaration of a variable:

variable variable_name : type [:= expression]

• A variable must be declared before use.

• The assignment is done with the operator ":=".

• The variable has an explicit initial value (if specified in the declaration) or implicit. In this case, it depends on the type. In general, the initial value is the leftmost value taken by the type.

VHDL: Signals

• Signals represent logical waveforms in the form of time/value pairs. They allow modeling the temporal characteristics of real signals and taking into account the different delays. They are essential for modeling concurrent behavior.

• A signal can be of any type.

• Declaration of a signal:

signal signal_name: type [:= expression] ;

• Initial value: same as for variables.

VHDL: Signal Characteristics

• A signal represents an equipotential.

• It must be declared before use.

• It can be declared:

  • In a package, it is then global.

  • In an entity, it is then common to all architectures of the entity.

  • In the architecture, it is then local.

• The assignment is done with the operator "<=".

VHDL: Comparator Example with std_logic Type

library ieee;
use ieee.std_logic_1164.all;
ENTITY eqcomp4 IS
PORT (
 a : IN STD_LOGIC_VECTOR(3 downto 0);
 b : IN STD_LOGIC_VECTOR(3 downto 0);
 aeqb : OUT STD_LOGIC
);
END eqcomp4;
ARCHITECTURE logique OF eqcomp4 IS
BEGIN
 aeqb <= '1' WHEN ( a = b ) ELSE '0';
END logique;

VHDL: Entity Declaration Syntax

entity entity_name is
    [generic(generic_list)]
    [port(port_list)]
end [entity] entity_name;

VHDL: Entity declaration Examples

entity full_adder is
    port(
        X, Y, Cin: in bit;
        Cout, Sum: out bit
    );
end full_adder;

entity comparator is
    port(
        signal a : in bit_vector(7 downto 0);
        signal b : in bit_vector(7 downto 0);
        signal egal : out bit
    );
end comparator;

VHDL: Architecture declaration Syntax

architecture architecture_name of entity_name is
  {signal_declaration} |
  {constant_declaration}
  {type_declaration} |
  {component_declaration}
begin
  {concurrent_instruction}
end [architecture] architecture_name;

VHDL: Architecture zone of declaration

• Any architecture is associated with an entity.

• There can be several architectures associated with the same component.

• 2 architectures of the same component.

VHDL: Architecture description levels

• The ARCHITECTURE describes the operation of the black box declared in the ENTITY.

• VHDL allows different levels of description:

  • High level (behavioral): description of functionality, without reference to the underlying 'hardware'.

  • Low level (structural): description by using and interconnecting 'components' (e.g., logic gates), as for a schematic.

VHDL: Behavioral Description

architecture ARCH1 of COMPARATOR is
begin
    C <= '1' when (A=B) else '0';
end ARCH1;

architecture ARCH2 of COMPARATOR is
begin
    C <= not(A xor B);
end ARCH2;

VHDL: Structural Description

architecture ARCH3 of COMPARATOR is
    signal S : bit;
begin
    U0 : xor2 port map (A, B, S);
    U1 : inv port map (S, C);
end ARCH3;

• Internal signals are declared at the head of the architecture (same declaration as entity signals, without 'mode').

VHDL: Description Selection

• Behavioral descriptions are recommended.

• Behavioral:

aeqb <= '1' WHEN a = b ELSE '0';

• Structural (low level):

u0: xnor2 PORT MAP (a(0), b(0), xnr(0));
u1: xnor2 PORT MAP (a(1), b(1), xnr(1));
u2: xnor2 PORT MAP (a(2), b(2), xnr(2));
u3: xnor2 PORT MAP (a(3), b(3), xnr(3));
u4: and4 PORT MAP (xnr(0), xnr(1), xnr(2), xnr(3), aeqb);

VHDL: Components

• COMPONENT allows writing a program in structural form. It is necessary to declare and define the components of the function, then in the body of the architecture, simply connect them following a structural diagram.

• This definition must respect the following four steps:

  • This is done by the syntax COMPONENT … END COMPONENT;

  • Assign the connections of the diagram to the pins of the components.

  • PORT MAP is used.

    • Attribute the circuits to their ENTITY.

    • Behavioral definition of each associated component. Here we will proceed with a simple writing structure based around ENTITY and ARCHITECTURE.

• A component can be called multiple times in the same circuit. To differentiate these same components, it is necessary to give them an instance name. The call of a component is also called "instantiation".

VHDL: Component Syntax

COMPONENT COMPONENT_name is
    [local_generic_clause]
    [local_port_clause]
END COMPONENT;

Instantiation

instantiation_label: COMPONENT_name
    [PORT MAP local_port_list]

VHDL: Port Map

• PORT MAP is used to associate the pins of a COMPONENT with the signals of the assembly.

• Two methods of assignment are possible:

  • By associating names.

  • By associating positions.

Syntax

PORT MAP (pin_name => signal_name {, pin_name => signal_name});
PORT MAP (signal_name {, signal_name});

VHDL: Component declaration

COMPONENT xor2 IS
    PORT (
        i1 : IN STD_LOGIC;
        i2 : IN STD_LOGIC;
        y : OUT STD_LOGIC
    ) ;
END COMPONENT;

VHDL: Component instantiation

ul: xor2 PORT MAP (
            i1 => a,
            i2 => b,
            y => ul_out
        );

VHDL: Component remplacement

• The "Component" declaration has been replaced only by using the following instruction in the instantiation:

Inst_1: entity work.and_2

VHDL: Component example

• In this example, 2 instances of component "and2" are called to create a 3-input AND gate.

• There are two instances of the and2 component, inst1 and inst2, each mapping inputs (a, b) to an output (c, z, then s). The architecture, Behavioral, shows signals and the component setup within the and_3 entity.

VHDL: Example and XOR3

• Structural and dataflow examples for implementing XOR3, including signal and component declarations, with a discussion of interconnections using port maps.

VHDL: Exercice - Schematic Synthesis

• Describes synthesizing a circuit from a schematic, showing component declarations and signal assignments for a full adder.

VHDL: Full Adder Code

• VHDL code describing the behavior of AND2, OR2, and XOR2 gates.

• Code describing the structure of a full adder using component instantiations: xor2, or2, and and2.

VHDL: Generic

• When creating entity-architecture pair, it is valuable to allow certain parameters to be modified by the program using the component.

• These parameters, whose actual value may only be fixed when the component is instantiated, are called generic parameters.

Declaration & Instantiation

• A generic parameter is declared at the beginning of the entity, and may have a default value. The declaration is made by the instruction "generic" as follows:

generic (name: type [: = default-value]);

• The entity associated with the component must include the "generic" instruction to declare the parameter(s).

Exemple

generic (N=>2)

• At instantiation, the parameter can be modified by the instruction "generic map"

• The symbol => allows here to make the association of constants to generic parameters

Generic - example

Realize an "and" gate with three inputs and each input is a