Pipelining Notes

Pipelining Basics

  • Definition: Pipelining is an implementation technique overlapping multiple instructions in execution, akin to assembling products on an assembly line.
Key Aspects:
  • Each instruction is processed through multiple stages.
  • Stages operate simultaneously on different instructions, improving performance by increasing throughput.
  • Instructions maintain the same latency but are subject to hazards, which can affect performance.

Key Performance Metrics

  • Latency: Total time from start to finish for a single task.
  • Throughput: Number of completed tasks over a specified time period.
  • Example: In laundry, if each load takes 30 minutes, 4 washers lead to 8 loads/hour throughput, but the latency per load is 2 hours.

RISC-V Pipeline Stages

  1. IF (Instruction Fetch): Fetches instruction from memory.
  2. ID (Instruction Decode): Decodes the instruction and reads from registers.
  3. EX (Execute): Executes the operation or calculates the address.
  4. MEM (Memory Access): Accesses memory operand.
  5. WB (Write Back): Writes result back to the register.

Latency vs Throughput in Pipelining

  • Latency: Total time for a single instruction to pass through all pipeline stages.
  • Throughput: Total instructions processed per hour.
  • Pipelining enhances throughput but does not reduce latency for individual tasks.

Pipeline Hazards

  • Definition: Conditions that prevent the next instruction from executing in the next clock cycle.
Types of Hazards:
  1. Structural Hazards: Occur when multiple instructions need the same resource.
    • Example: If both instruction fetch and memory access need the same memory.
  2. Data Hazards: Occur when an instruction depends on data from a previous instruction that has not yet completed.
    • Addressed by forwarding (bypassing).
  3. Control Hazards: Branching in instructions necessitates knowledge about control flow, which can stall the pipeline.

Data Hazards and Solutions

  • Forwarding: Bypassing techniques to use data before it is officially written to registers.
  • Load-Use Hazard: Occurs when a subsequent instruction depends on the result of a load instruction that hasn't completed.
  • Example: ld x1, 0(x0) followed immediately by using the value of x1 in another instruction.

Code Scheduling to Avoid Stalls

  • Altering instruction order to minimize reliance on a previous instruction’s result before completion.
  • Example: Restructuring code can avoid potential hazards by creating a buffer with independent instructions in between.

Control Hazards and Prediction

  • When a branch instruction is executed, the pipeline may not know which instruction to fetch next, causing stalling.
  • Branch Prediction: Strategies to predict the outcome of branches to maintain pipeline flow without stalls.
  • Techniques:
    • Static Prediction: Assumes certain types of branches behave consistently (e.g., loops as taken).
    • Dynamic Prediction: Uses historic behavior to predict future branch behavior.

Pipelined Data Path Insights

  • Pipeline registers are essential for holding data between stages to ensure proper sequencing and avoid conflicts.
  • Control signals are derived from the instructions and are crucial for guiding the execution flow appropriately across different pipeline stages.

Efficiency Considerations

  • A longer pipeline can enhance throughput by using shorter cycles, improving overall execution speed even if individual instruction latency remains the same.
  • Certain instructions, such as ALU operations and branches, may need special consideration to optimize their handling and minimize delays while maximizing throughput through streamlined design.

Conclusion

  • Pipelining significantly boosts the processor's throughput by executing several instructions in parallel, despite increases in complexity and potential hazards that must be managed. Understanding these principles is critical for designing efficient CPUs and optimizing performance in computing architectures.