PHYSICS140 - Lecture Notes on JK Flip Flop and Counter Design
Recap of JK Flip Flop and Its Enhancements
Introduction to the JK Flip Flop
Basic Components
Inputs: J and K
Outputs: Q and not Q
Edge Triggered Clock: Indicates when to update Q based on J and K inputs.
Asynchronous Inputs
Two additional inputs: Not Preset (active low) and Not Clear (active low)
Not Preset sets the output Q high regardless of J and K states when low.
Not Clear resets the output Q low regardless of J and K states when low.
Timing Diagram of JK Flip Flop
Characteristics of the Outputs
In green highlighted regions (when Not Preset and Not Clear are low), Q is forced to high or low.
When Not Preset is low, Q remains high regardless of clock and J & K inputs.
When Not Clear is low, Q remains low regardless of clock and J & K inputs.
At all other times, transitions in Q occur based on the clock (synchronous operation).
Design Example: Master-Slave Flip Flop
Operation of Master-Slave Flip Flop
Composed of two gated SR latches that update based on the clock.
First latch operates on the clock's high state (S goes through to Q1).
Second latch operates when the first latch's clock goes low, allowing Q1 to determine Q's state.
Postponed Inputs: Intermediate states between latches must be observed to prevent glitches.
Counters Overview
Types of Counter
Down Counter: Positive edge triggered, transitions on rising edges of the clock.
Up Counter: Negative edge triggered, delays due to NOT gates cause output states to differ.
Cascading Counters: Connecting several flip flops, where the output of one is the input trigger for another.
Definitions and Classifications
Combinatorial Circuits vs. Sequential Circuits
Combinatorial: Outputs depend solely on present inputs.
Sequential: Outputs depend on present inputs and the current or previous state.
Types of Sequential Circuits
Asynchronous: Outputs not synchronized to the clock.
Synchronous: Outputs synchronized to the clock (strict definition requires outputs change in unison with clock pulses).
Asynchronous Counters and Their Limitations
Propagation Delays: Each flip-flop introduces a time delay, possibly causing incorrect readings if checked too soon after clock transitions.
Ripple Counters: Type of asynchronous counters with differing propagation delays that can yield faulty outputs.
Example: Binary Up Counter: A 3-bit counter can count from zero to seven with propagation delays causing potential reading errors.
Asynchronous Decade Counter Construction
Goal: Count from 0 to 9.
Circuit Design: Utilizes 4 JK flip flops to generate a binary counter.
Detection of Decimal 10: Using a logic gate (NOR) to reset once the counter detects the state for ten.
State is represented as Q3=1, Q2=0, Q1=1, Q0=0.
Issues: As before, acknowledge minor glitches during the detection phase.
Design Example: Modulo 5 Counter
Conclusion: Create a counter that counts using 3 JK flip flops resetting at decimal five by detecting the inputs properly through logic gates.
The JK Flip Flop is an edge-triggered memory device utilizing inputs J and K, which control the output Q and its inverse. It has asynchronous inputs: Not Preset (sets Q high when low) and Not Clear (sets Q low when low). The timing diagram indicates that transitions in Q happen based on the clock, with specific states imposed by the asynchronous inputs.
A Master-Slave Flip Flop consists of two gated SR latches that update asynchronously when clock states change to ensure stability, avoiding glitches. Counters can be classified as Down (rising edges) or Up (falling edges), with cascading designs creating complex counting mechanisms.
Combinatorial circuits rely on present inputs for outputs, while sequential circuits account for current and previous states. Asynchronous counters can suffer from propagation delays affecting output accuracy, exemplified by ripple counters. Asynchronous decade counters are built using JK flip flops, detecting decimal states through logic gates. The Modulo 5 counter example illustrates how to design a counter resetting at five using proper input detection.
Propagation delay is the time it takes for a signal to travel through a circuit or component after a clock transition. In the context of flip-flops or counters, each flip-flop introduces a time delay before it can output the correct state in response to an input change. This delay is crucial in synchronous systems as it can lead to incorrect readings if the outputs are checked too soon after a clock transition, contributing to phenomena such as race conditions or glitches in asynchronous counters. Ripple counters, for example, can experience varying propagation delays due to the cascading effect, which can result in faulty outputs and unreliable counting sequences.
Recap of JK Flip Flop and Its Enhancements
Introduction to the JK Flip Flop
Basic Components
Inputs: J and K
Outputs: Q and not Q
Edge Triggered Clock: Indicates when to update Q based on J and K inputs.
Asynchronous Inputs
Two additional inputs: Not Preset (active low) and Not Clear (active low)
Not Preset sets the output Q high regardless of J and K states when low.
Not Clear resets the output Q low regardless of J and K states when low.
Timing Diagram of JK Flip Flop
Characteristics of the Outputs
In green highlighted regions (when Not Preset and Not Clear are low), Q is forced to high or low.
When Not Preset is low, Q remains high regardless of clock and J & K inputs.
When Not Clear is low, Q remains low regardless of clock and J & K inputs.
At all other times, transitions in Q occur based on the clock (synchronous operation).
Design Example: Master-Slave Flip Flop
Operation of Master-Slave Flip Flop
Composed of two gated SR latches that update based on the clock.
First latch operates on the clock's high state (S goes through to Q1).
Second latch operates when the first latch's clock goes low, allowing Q1 to determine Q's state.
Postponed Inputs: Intermediate states between latches must be observed to prevent glitches.
Counters Overview
Types of Counters
Down Counter: Positive edge triggered, transitions on rising edges of the clock.
Up Counter: Negative edge triggered, delays due to NOT gates cause output states to differ.
Cascading Counters: Connecting several flip flops, where the output of one is the input trigger for another.
Definitions and Classifications
Combinatorial Circuits vs. Sequential Circuits
Combinatorial: Outputs depend solely on present inputs.
Sequential: Outputs depend on present inputs and the current or previous state.
Types of Sequential Circuits
Asynchronous: Outputs not synchronized to the clock.
Synchronous: Outputs synchronized to the clock (strict definition requires outputs change in unison with clock pulses).
Asynchronous Counters and Their Limitations
Propagation Delays: Each flip-flop introduces a time delay, possibly causing incorrect readings if checked too soon after clock transitions.
Ripple Counters: Type of asynchronous counters with differing propagation delays that can yield faulty outputs.
Example: Binary Up Counter: A 3-bit counter can count from zero to seven with propagation delays causing potential reading errors.
Asynchronous Decade Counter Construction
Goal: Count from 0 to 9.
Circuit Design: Utilizes 4 JK flip flops to generate a binary counter.
Detection of Decimal 10: Using a logic gate (NOR) to reset once the counter detects the state for ten. State is represented as Q3=1, Q2=0, Q1=1, Q0=0.
Issues: As before, acknowledge minor glitches during the detection phase.
Design Example: Modulo 5 Counter
Conclusion: Create a counter that counts using 3 JK flip flops resetting at decimal five by detecting the inputs properly through logic gates.
The JK Flip Flop is an edge-triggered memory device utilizing inputs J and K, which control the output Q and its inverse. It has asynchronous inputs: Not Preset (sets Q high when low) and Not Clear (sets Q low when low). The timing diagram indicates that transitions in Q happen based on the clock, with specific states imposed by the asynchronous inputs.
A Master-Slave Flip Flop consists of two gated SR latches that update asynchronously when clock states change to ensure stability, avoiding glitches.
Example of a Master-Slave Flip Flop: Consider a smartphone screen lock mechanism where the first latch temporarily stores input (e.g., a fingerprint), while the second latch activates the screen only once the first input is confirmed, preventing flicker in response to accidental touches.
Counters can be classified as Down (rising edges) or Up (falling edges), with cascading designs creating complex counting mechanisms.