Flip-Flop Conversion – Lecture 14

Key Principles of Flip-Flop Conversion

• Goal: implement the behaviour of a desired (target) flip-flop using a different (available) flip-flop by creating suitable combinational logic for the available FF’s inputs.

• Methodology: The process involves two key tools:

  • 1. Conversion (Excitation) Table Construction: This table maps the behavior of the desired (target) flip-flop onto the excitation requirements of the available flip-flop.

    • It lists all possible combinations of the target FF's inputs (e.g., J, K, D, T), the present state ( $Q<em>p$ ), the desired next state ( $Q</em>{p+1}$ , derived from the target FF's characteristic table), and the required inputs for the available FF needed to achieve that $Q<em>{p+1}$ from $Q</em>p$ (derived from the available FF's excitation table).

    • Treat the input(s) of the target FF as primary variables, alongside $Q_p$.

  • 2. K-map Minimization: For each input of the available flip-flop (e.g., S, R for SR; J, K for JK), a separate K-map is populated using the corresponding values (0, 1, or X for don't care conditions) from the conversion table.

    • The variables for these K-maps are the target FF's inputs and $Q_p$.

    • Minimal Boolean expressions for each input of the available FF are then derived from these K-maps.

  • These expressions are then implemented with combinational logic gates, and connected to the clock of the available FF.

• Typical reasons for conversion - Re-use of standard JK, D or T ICs to emulate other types.

  • Reduce gate count in a given design.

  • Provide level-sensitive, edge-triggered or master–slave behaviour that is not natively present.

Catalogue of Conversions Covered

• $\text{SR} \;\rightarrow\; \text{JK}$

• $\text{JK} \;\rightarrow\; \text{SR}$

• $\text{SR} \;\rightarrow\; \text{D}$

• $\text{D} \;\rightarrow\; \text{SR}$

• $\text{JK} \;\rightarrow\; \text{T}$

• $\text{JK} \;\rightarrow\; \text{D}$

• $\text{D} \;\rightarrow\; \text{JK}$

Detailed Conversion Notes

1. SR ➜ JK

• Variables: $J,\;K,\;Q_p$

• Conversion table built from SR excitation requirements.

• K-map minimisation yields - $S = JQ_p$

  • $R = K\overline{Q_p}$

• Implementation: - Design two AND gates feeding SR inputs, each gated by $Q<em>p$ or $\overline{Q</em>p}$ as indicated, then ORed with the external $J$ or $K$ respectively.

  • Clock of JK becomes the clock of the SR.

• Practical note: ensures all $SR=11$ combinations are eliminated (mapped to don’t-care X).

2. JK ➜ SR

• Because SR has only Set and Reset, derive them directly from JK.

• K-maps give very simple results: - $J = S$

  • $K = R$

• Therefore, wire J to S and K to R; the clock is shared.

• Caution: states where $S=R=1$ are invalid and are flagged as X in the conversion table.

3. SR ➜ D

• Desired: single data input $D$ reproduced by SR.

• Table shows four legal SR combinations; K-maps yield - $S = D$

  • $R = \overline{D}$

• Implementation: - Direct line from $D$ to S.

  • Inverter from $D$ to R.

  • Guarantees exactly one of S/R asserted per cycle.

4. D ➜ SR

• Objective: generate S and R that reproduce the next state behaviour of a D flip-flop.

• Excitation table & K-map provide single equation (because SR has two inputs but you get one combined condition): - $D = S + RQ_p$

  • Rearranged to find required signals:
    
    

    • Set when $S = D\;\land\; \overline{Q<em>p}$ • Reset when $R = \overline{D} \land Q</em>p$

• A minimal implementation is: - S = $D \;\overline{Q_p}$

  • R = $\overline{D}Q_p$

• Invalid condition $S=R=1$ mapped to X in the table.

5. JK ➜ T

• A T flip-flop toggles on $T=1$ and holds on $T=0$.

• From JK truth table we realise: - Toggle occurs when $J=K=1$, Hold when $J=K=0$.

• Therefore a single line solution: - $J = T$

  • $K = T$

• Implementation: tie both JK inputs together to the external $T$.

6. JK ➜ D

• Need next state $Q_{p+1} = D$ irrespective of present state.

• K-map analysis shows - $J = D$

  • $K = \overline{D}$

• Realisation: - Feed $D$ to J, the complement of $D$ (via inverter) to K.

7. D ➜ JK

• Treat $J$ and $K$ as minimisation outputs when the available FF is JK.

• K-map result: - $D = J\overline{Q<em>p} + \overline{K}Q</em>p$

  • Solving, we can choose a symmetrical implementation:
    
    

    • $J = D\overline{Q<em>p}$ • $K = \overline{D}Q</em>p$

• Alternate, gate-level approach: - Use two ANDs and one OR to meet the equation above.

Common Themes & Observations

• Every conversion keeps the clocking edge identical; only the combinational front-end changes.

• Don’t-care (X) entries in tables immensely simplify K-map reduction and gate count.

• Illegal SR state $S=R=1$ is either avoided (marked X) or never produced by the equations.

• Converting upwards (single-input ➜ multi-input) often requires gating with $Q_p$; converting downwards (multi-input ➜ single-input) usually involves tying inputs together or inverting one of them.

• Equations can be implemented in NAND/NOR logic for easier IC realisation.

Real-World Relevance & Design Tips

• Digital designers rarely keep inventories of every FF type; these conversions permit flexible use of standard ICs like 74LS74 (JK), 74LS73 (JK master–slave) or 74LS74 (D).

• FPGA tool-flows apply the same principles when mapping HDL-described flip-flops onto the fabric’s primitive elements.

• Ethically, be aware that mis-using conversions without understanding metastability or timing can lead to latent design faults.

• Always verify with simulation and, if necessary, timing analysis to ensure that combinational delay from conversion logic does not violate setup/hold requirements.