Basic Computer Organization and Design

5-1 Instruction Codes

• Introduces a basic computer and specifies its operation using register transfer statements.
• The computer's organization is defined by its internal registers, timing and control structure, and instruction set.
• The design of the computer is carried out in detail.
• The basic computer is simple to demonstrate the design process without significant complications.
• The internal organization of a digital system is defined by the sequence of microoperations on data stored in registers.
• A general-purpose digital computer executes various microoperations and can be instructed on what sequence to perform.
• A program is a set of instructions that specify operations, operands, and the processing sequence.
• Data-processing tasks can be altered by specifying new programs or using the same instructions with different data.

5-2 Computer Instruction

• A computer instruction is a binary code that specifies a sequence of microoperations.
• Instruction codes and data are stored in memory.
• The computer reads instructions from memory and places them in a control register.
• The control interprets the binary code and executes it by issuing microoperations.
• Every computer has its own unique instruction set.
• The stored program concept, the ability to store and execute instructions, is a key property of general-purpose computer

5-3 Instruction Code

• An instruction code is a group of bits that instructs the computer to perform a specific operation.
• It is divided into parts, each with its own interpretation.
• The most basic part is the operation code, which defines operations like add, subtract, etc.
• The number of bits for the operation code depends on the total number of operations available.
• For $2^n$ or fewer distinct operations, at least $n$ bits are required for the operation code.
• Example: A computer with 64 distinct operations (e.g., ADD) requires a 6-bit operation code.
• The control unit decodes the operation code and issues control signals to execute microoperations.

5-4 Computer Operation vs Microoperation

• A computer operation is part of an instruction in memory, a binary code for a specific action.
• The control unit interprets operation code bits and issues control signals to initiate microoperations in registers.
• For every operation code, the control issues a sequence of microoperations for hardware implementation.
• An operation code is sometimes called a macrooperation as it specifies a set of micro-operations.
• The operation part of an instruction specifies the operation to be performed on data in processor registers or memory.
• An instruction code must specify the operation, the location of operands (registers or memory words), and where to store the result.
• Memory words are specified by their address, and processor registers are specified by binary codes.
• Instruction code formats vary, with each computer having its own format conceived by designers.

5-5 Stored Program Organization

• The simplest computer organization involves one processor register and a two-part instruction code.
• The first part specifies the operation, and the second specifies an address.
• The memory address indicates where to find an operand in memory.
• Instructions are stored in one memory section, and data in another.
• For a memory unit with 4096 words, 12 bits are needed to specify an address since $(2^{12} = 4096)$.
• If each instruction code is stored in a 16-bit memory word, 4 bits are available for the opcode, and 12 bits for the operand address.
• The control reads a 16-bit instruction and a 16-bit operand, then executes the operation.
• Computers with a single-processor register usually call it an accumulator (AC).
• The operation is performed using the memory operand and the content of AC.
• If an operation doesn't need an operand from memory, the instruction bits can be used for other purposes.
• Examples: clear AC, complement AC, and increment AC operate on data in the AC register.
• For these operations, bits 0-11 are not needed for specifying a memory address and can specify other operations.

5-6 Immediate vs. Direct vs. Indirect Address

• Immediate Operand: The address bits of an instruction code are used as the actual operand.
• Direct Address: The second part of the instruction code specifies the address of an operand.
• Indirect Address: The bits in the second part of the instruction designate an address of a memory word containing the operand's address.
• One bit of the instruction code can distinguish between direct and indirect addresses.
• Instruction format: 3-bit opcode, 12-bit address, and an indirect address mode bit (I).
• I = 0 for direct address, I = 1 for indirect address.
• Direct address instruction: I = 0, opcode specifies an ADD instruction, address part is 457.
• The control finds the operand in memory at address 457 and adds it to the content of AC.
• Indirect address instruction: I = 1, address part is 300.
• The control goes to address 300 to find the address of the operand, which is 1350.
• The operand found in address 1350 is then added to the content of AC.
• The indirect address instruction needs two memory references to fetch an operand.
• Effective Address: The address of the operand in a computation-type instruction or the target address in a branch-type instruction.
• Effective address in direct addressing is 457, while in indirect addressing, it is 1350.
• Direct and indirect addressing modes are used in the computer presented in the chapter.
• The memory word holding the address of the operand in an indirect address instruction serves as a pointer to an array of data.

5-7 Computer Registers

• Computer instructions are stored in consecutive memory locations and executed sequentially.
• The control reads an instruction from memory and executes it, then reads the next instruction in sequence.
• Instruction sequencing needs a counter to calculate the address of the next instruction after execution.
• A register is needed in the control unit to store the instruction code after being read from memory.
• The computer needs processor registers for manipulating data and a register for holding a memory address.
• Configurations include: Data Register (DR), Address Register (AR), Accumulator (AC), Instruction Register (IR), Program Counter (PC), Temporary Register (TR), Input Register (INPR), and Output Register (OUTR).

5-8 Registers Descriptions

• DR (Data Register): Holds the operand read from memory (16 bits).
• AR (Address Register): Holds the address for memory (12 bits).
• AC (Accumulator): General-purpose processing register (16 bits).
• IR (Instruction Register): Holds the instruction code (16 bits).
• PC (Program Counter): Holds the address of the next instruction to be read (12 bits).
• TR (Temporary Register): Holds temporary data during processing (16 bits).
• INPR (Input Register): Holds input character (8 bits).
• OUTR (Output Register): Holds output character (8 bits).
• PC goes through a counting sequence, causing the computer to read sequential instructions.
• Instruction words are read and executed in sequence unless a branch instruction is encountered.
• To read an instruction, the content of PC is taken as the address for memory, and a memory read cycle is initiated.
• PC is incremented by one to hold the address of the next instruction in sequence.
• Two registers, INPR and OUTR, are used for input and output.
• INPR receives an 8-bit character from an input device, and OUTR holds an 8-bit character for an output device.

5-9 Common Bus System

• The basic computer has eight registers, a memory unit, and a control unit.
• Paths are needed to transfer information between registers and between memory and registers.
• A common bus is a more efficient scheme for transferring information in a system with many registers.
• The outputs of seven registers and memory are connected to the common bus.
• The specific output selected for the bus lines is determined from the selection variables $S<em>2$, $S</em>1$, and $S_0$.
• The lines from the common bus are connected to the inputs of each register and the data inputs of the memory.
• The particular register whose LD (load) input is enabled receives the data from the bus during the next clock pulse transition.
• The memory receives the contents of the bus when its write input is activated.
• The memory places its 16-bit output onto the bus when the read input is activated and $S<em>2S</em>1S_0 = 111$.

5-10 Registers bits

• Four registers (DR, AC, IR, TR) have 16 bits each.
• Two registers (AR, PC) have 12 bits each.
• When AR or PC are applied to the 16-bit common bus, the four most significant bits are set to 0’s.
• The input register INPR and the output register OUTR have 8 bits each.
• INPR provides information to the bus, but OUTR can only receive information from the bus.
• The 16 lines of the common bus receive information from six registers and the memory unit.
• The bus lines are connected to the inputs of six registers and the memory.
• Five registers (DR, PC, AR, IR, TR) have three control inputs: LD (load), INR (increment), and CLR (clear).
• The increment operation is achieved by enabling the count input of the counter.
• Two registers (INPR, OUTR) have only a LD input.
• The input data and output data of the memory are connected to the common bus, but the memory address is connected to AR.
• AR must always be used to specify a memory address.

5-11 AC (Accumulator)

• 16 inputs of AC come from an adder and logic circuit with three sets of inputs.
• One set of 16-bit inputs come from the outputs of AC.
• Another set of 16-bit inputs come from the data register DR.
• A third set of 8-bit inputs come from the input register INPR.
• The result of an addition is transferred to AC, and the end carry-out of the addition is transferred to flip-flop E.
• The two microoperations DR ← AC and AC ← DR can be executed at the same time.
• This can be done by placing the content of AC on the bus (with $S<em>2S</em>1S_0 = 100$), enabling the LD (load) input of DR,
• transferring the content of DR through the adder and logic circuit into AC, and enabling the LD (load) input of AC, all during the same clock cycle.
• The two transfers occur upon the arrival of the clock pulse transition at the end of the clock cycle.

5-12 Computer Instructions Formats

• The basic computer has three instruction code formats, each with 16 bits.
• The operation code (opcode) part of the instruction contains three bits.
• A memory-reference instruction uses 12 bits to specify an address and one bit to specify the addressing mode I.
• I = 0 for direct address and I = 1 for indirect address.
• Register-reference instructions are recognized by the operation code 111 with a 0 in the leftmost bit (bit 15).
• A register-reference instruction specifies an operation on or a test of the AC register.
• Input–output instructions are recognized by the operation code 111 with a 1 in the leftmost bit of the instruction.
• The type of instruction is recognized by the computer control from the four bits in positions 12 through 15 of the instruction.
• If the three opcode bits in positions 12 though 14 are not equal to 111, the instruction is a memory-reference type.

5-13 Total number of instruction

• Only three bits of the instruction are used for the operation code, restricting the computer to a maximum of eight distinct operations.
• The total number of instructions chosen for the basic computer is equal to 25.

5-14 Instruction Set Completeness

• A computer should have a set of instructions to construct machine language programs to evaluate any computable function.
• A set of instructions is complete if the computer includes a sufficient number of instructions in each of the following categories:
  • Arithmetic, logical, and shift instructions
  • Instructions for moving information to and from memory and processor registers
  • Program control instructions together with instructions that check status conditions
  • Input and output instructions

5-15 Instruction Types

• Arithmetic, logical, and shift instructions provide computational capabilities for processing data.
• Moving information between memory and processor registers is necessary because computations are done in processor registers.
• Decision-making capabilities are an important aspect of digital computers.
• Program control instructions such as branch instructions are used to change the sequence in which the program is executed.
• Input and output instructions are needed for communication between the computer and the user.

5-16 Instruction Set Description

• The instructions constitute a minimum set that provides all the capabilities mentioned above.
• One arithmetic instruction, ADD, and two related instructions, complement AC (CMA) and increment AC (INC).
• With these three instructions, binary numbers can be added and subtracted when negative numbers are in signed-2’s complement representation.
• The circulate instructions, CIR and CIL, can be used for arithmetic shifts as well as any other type of shifts desired.
• Multiplication and division can be performed using addition, subtraction, and shifting.
• Three logic operations: AND, complement AC (CMA), and clear AC (CLA).
• The AND and complement provide a NAND operation.
• Moving information from memory to AC is accomplished with the load AC (LDA) instruction.
• Storing information from AC into memory is done with the store AC (STA) instruction.
• The branch instructions BUN, BSA, and ISZ, together with the four skip instructions, provide capabilities for program control and checking of status conditions.
• The input (INP) and output (OUT) instructions cause information to be transferred between the computer and external devices.

5-17 instruction efficiency limitation

• The set of instructions for the basic computer is complete but not efficient because frequently used operations are not performed rapidly.
• An efficient set of instructions will include instructions such as subtract, multiply, OR, and exclusive-OR.

5-18 Timing and Control

• The timing for all registers in the basic computer is controlled by a master clock generator.
• The clock pulses are applied to all flip-flops and registers in the system, including the flip-flops and registers in the control unit.
• The clock pulses do not change the state of a register unless the register is enabled by a control signal.
• The control signals are generated in the control unit and provide control inputs for the multiplexers in the common bus, control inputs in processor registers, and microoperations for the accumulator.

5-19 Control Organization

• Two major types of control organization: hardwired control and microprogrammed control.

5-20 Hardwired Control

• Implemented with gates, flip-flops, decoders, and other digital circuits.
• Advantage: can be optimized to produce a fast mode of operation.
• Disadvantage: requires changes in wiring among the various components if the design has to be modified or changed.

5-21 Microprogrammed Control

• Control information is stored in a control memory.
• Control memory is programmed to initiate the required sequence of microoperations.
• Changes or modifications can be done by updating the microprogram in control memory.

5-22 Control Unit

• Consists of two decoders, a sequence counter, and a number of control logic gates.
• An instruction read from memory is placed in the instruction register (IR).
• The instruction register is divided into three parts: the I bit, the operation code, and bits 0 through 11.
• The operation code in bits 12 through 14 are decoded with a 3 8 decoder.
• The outputs of the decoder are designated by the symbols $D<em>0$ through $D</em>7$.
• Bit 15 of the instruction is transferred to a flip-flop designated by the symbol I.
• Bits 0 through 11 are applied to the control logic gates.
• The 4-bit sequence counter can count in binary from 0 through 15.
• The outputs of the counter are decoded into 16 timing signals $T<em>0$ through $T</em>{15}$.
• The sequence counter SC can be incremented or cleared synchronously.
• SC is incremented to provide the sequence of timing signals.
• The counter is cleared to 0, causing the next active timing signal to be $T_0$.
• Example: At time $T<em>4$, SC is cleared to 0 if decoder output $D</em>3$ is active: $D<em>3T</em>4: SC ← 0$.
• A memory read or write cycle will be initiated with the rising edge of a timing signal.

5-23 Clock Transition

• According to the assumption, a memory read or write cycle initiated by a timing signal will be completed by the time the next clock goes through its positive transition.
• The clock transition will then be used to load the memory word into a register.

5-24 Instruction Cycle

• A program residing in the memory unit consists of a sequence of instructions.
• The program is executed in the computer by going through a cycle for each instruction.
• Each instruction cycle is subdivided into a sequence of subcycles or phases:
  • Fetch an instruction from memory.
  • Decode the instruction.
  • Read the effective address from memory if the instruction has an indirect address.
  • Execute the instruction.
• Upon the completion of step 4, the control goes back to step 1 to fetch, decode, and execute the next instruction.
• This process continues indefinitely unless a HALT instruction is encountered.

5-25 Fetch and Decode

• Initially, the program counter PC is loaded with the address of the first instruction in the program.
• The sequence counter SC is cleared to 0, providing a decoded timing signal $T_0$.
• After each clock pulse, SC is incremented by one, so that the timing signals go through a sequence $T<em>0$, $T</em>1$, $T_2$, and so on.
• The microoperations for the fetch and decode phases can be specified by the following register transfer statements:
  • $T_0: AR ← PC$
  • $T_1: IR ← M [AR], PC ← PC + 1$
  • $T<em>2: D</em>0, . . . , D_7 ← Decode IR(12–14), AR ← IR(0–11), I ← IR(15)$

5-26 Type of instruction

• During time $T_3$, the control unit determines the type of instruction that was just read from memory.
  • Decoder output $D_7$ is equal to 1 if the operation code is equal to binary 111.
  • If $D_7 = 1$, the instruction must be a register-reference or input–output type.
  • If $D_7 = 0$, the operation code must be one of the other seven values 000 through 110, specifying a memory-reference instruction.
• If $D_7 = 0$ and $I = 1$, there is a memory-reference instruction with an indirect address.
• The microoperation for the indirect address condition can be symbolized by: $AR ← M [AR]$
• When a memory-reference instruction with $I = 0$ is encountered, it is not necessary to do anything since the effective address is already in AR.
• A register-reference or input-output instruction can be executed with the clock associated with timing signal $T_3$.
• After the instruction is executed, SC is cleared to 0 and control returns to the fetch phase with $T_0 = 1$.

5-27 Register-Reference Instructions

• Register-reference instructions are recognized by the control when $D_7 = 1$ and $I = 0$.
• These instructions use bits 0 through 11 of the instruction code to specify one of 12 instructions.
• Each control function needs the Boolean relation $D<em>7I'T</em>3$, which is designated by the symbol r.
• The execution of a register-reference instruction ends at time $T_3$.
• The sequence counter SC is cleared to 0, and the control goes back to fetch the next instruction with timing signal $T_0$.
• When the sign bit in AC (15) = 0, AC is positive; when AC(15) = 1, it is negative.
• The HLT instruction clears a start-stop flip-flop S and stops the sequence counter from counting. It must be set manually.

5-28 AND to AC

• This is an instruction that performs the AND logic operation on pairs of bits in AC and the memory word specified by the effective address.
• The result of the operation is transferred to AC. The microoperations that execute this instruction are:
  • $D<em>0T</em>4: DR ← M [AR]$
  • $D<em>0T</em>5: AC ← AC \,AND\, DR, SC ← 0$

5-29 ADD to AC

• This instruction adds the content of the memory word specified by the effective address to the value of AC.
• The sum is transferred into AC, and the output carry Cout is transferred to the E (extended accumulator) flip-flop.
• The microoperations needed to execute this instruction are
  • $D<em>1T</em>4: DR ← M [AR]$
  • $D<em>1T</em>5: AC ← AC + DR, E ← C_{out}, SC ← 0$

5-30 LDA (Load to AC)

• This instruction transfers the memory word specified by the effective address to AC.
• The microoperations needed to execute this instruction are
  • $D<em>2T</em>4: DR ← M [AR]$
  • $D<em>2T</em>5: AC ← DR, SC ← 0$

5-31 STA (Store AC)

• This instruction stores the content of AC into the memory word specified by the effective address.
• The microoperation is: $D<em>3T</em>4: M [AR] ← AC, SC ← 0$

5-32 BUN (Branch Unconditionally)

• This instruction transfers the program to the instruction specified by the effective address.
• The instruction is executed with one microoperation:
  $D<em>4T</em>4: PC ← AR, SC ← 0$

5-33 BSA (Branch and Save Return Address)

• The BSA instruction stores the address of the next instruction in sequence (which is available in PC) into a memory location specified by the effective address.
• The effective address plus one is then transferred to PC to serve as the address of the first instruction in the subroutine.
• The BSA instruction performs the function usually referred to as a subroutine call.
• The indirect BUN instruction at the end of the subroutine performs the function referred to as a subroutine return.
• To use the memory and the bus properly, the BSA instruction must be executed with a sequence of two microoperations:
  • $D<em>5T</em>4: M [AR] ← PC, AR ← AR + 1$
  • $D<em>5T</em>5: PC ← AR, SC ← 0$

5-34 ISZ (Increment and Skip if Zero)

• This instruction increments the word specified by the effective address, and if the incremented value is equal to 0, PC is incremented by 1.
• The microoperations requires:
  • $D<em>6T</em>4: DR ← M [AR]$
  • $D<em>6T</em>5: DR ← DR + 1$
  • $D<em>6T</em>6: M [AR] ← DR, if (DR = 0) then (PC ← PC + 1), SC ← 0$
• The computer can be designed with a 3-bit sequence counter.
• The reason for using a 4-bit counter for SC is to provide additional timing signals for other instructions.

5-35 Input Output Organization

• The terminal sends and receives serial information with each quantity of information having eight bits of an alphanumeric code.
• The serial information from the keyboard is shifted into the input register INPR.
• The serial information for the printer is stored in the output register OUTR.
• INPR consists of eight bits and holds an alphanumeric input information.
• The 1-bit input flag FGI is a control flip-flop, is set to 1 when new information is available, and is cleared to 0 when the information is accepted by the computer.
• The output register OUTR works similarly but the direction of information flow is reversed.

5-36 Input Output Instruction

• Input and output instructions are needed for transferring information to and from AC register, for checking the flag bits, and for controlling the interrupt facility.
• Each control function needs a Boolean relation $D<em>7IT</em>3$, which we designate for convenience by the symbol p.

5-37 Program Interrupt

• Is an alternative to the programmed controlled procedure.
• While the computer is running a program, it does not check the flags. However, when a flag is set, the computer is momentarily interrupted from proceeding with the current program and is informed of the fact that a flag has been set.
• An interrupt flip-flop R is included in the computer.
• If R’s value is 1 it goes through an interrupt cycle instead of an instruction cycle.

5-38 Interrupt Cycle

• The interrupt cycle is a hardware implementation of a branch and save return address operation.
• The return address available in PC is stored in a specific location where it can be found later when the program returns to the instruction at which it was interrupted.

5-39 Modified Fetch Phase

• We will AND the three timing signals with $R'$ so that the fetch and decode phases. The control will go through a fetch phase only if $R = 0$.
• Otherwise, if $R = 1$, The control will go through an interrupt cycle
• The interrupt cycle stores the return address (available in PC ) into memory location 0, branches to memory location 1, and clears IEN, R, and SC to 0.
• During the first timing signal AR is cleared to 0, and the content of PC is transferred to the temporary register TR.
• With the second timing signal, the return address is stored in memory at location 0 and PC is cleared to 0.
• The beginning of the next instruction cycle has the condition $R'T_0$ and the content of PC is equal to 1.

5-40 Computer Description

• The interrupt flip-flop R may be set at any time during the indirect or execute phases. Control returns to timing signal $T_0$ after SC is cleared to 0.
• If $R = 1$, the computer goes through an interrupt cycle. If $R = 0$, the computer goes through an instruction cycle.
• The register transfer statements describe in a concise form the internal organization of the basic computer.
• A register transfer language is useful not only for describing the internal organization of a digital system but also for specifying the logic circuits needed for its design.

5-41 design the components of basic computer

• The basic computer consists of the following hardware components:
  • A memory unit with 4096 words of 16 bits each
  • Nine registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
  • Seven flip-flops: I, S, E, R, IEN, FGI, and FGO
  • Two decoders: a 3 8 operation decoder and a 4 16 timing decoder
  • A 16-bit common bus
  • Control logic gates
  • Adder and logic circuit connected to the input of AC

5-42 Control Logic

• The inputs to this circuit come from the two decoders, the I flip-flop, and bits 0 through 11 of IR. and the bits to check certain flip flop.
• The outputs of the control logic circuit are:
  • Signals to control the inputs of the nine registers
  • Signals to control the read and write inputs of memory
  • Signals to set, clear, or complement the flip-flops
  • Signals for S2, S1, and S0 to select a register for the bus
  • Signals to control the AC adder and logic circuit

5-43 LD(AR)

• The logic gates associated with the read input of memory is derived by scanning. can be represented
  Read = $R'T<em>1 + D'</em>7I + (D<em>0 + D</em>1 + D<em>2 + D</em>6)T_4$

5-44 IEN (Interrupt Enable Flip-Flop)

• Use a JK flip-flop for IEN. Control gate logic is: $</li> <li>When$x1 = 1$, the value of$S2S1S0$must be 001 and the output of AR will be selected for the bus<br /> S0 =$x1 + x3 + x5 + x7$<br /> S1 =$x2 + x3 + x6 + x7$<br /> S2 =$x4 + x5 + x6 + x7$$
  In order to design the logic associated with AC, it is necessary to go over the register transfer statements to design flip flop.