CAIE AS Computer Science – Processor Fundamentals & Assembly Language

CPU Architecture (Von Neumann Model)

  • Concept

    • John von Neumann recognized that data and programs share the same physical memory.

    • Architecture uses one single processor that follows a linear \text{fetch}\rightarrow\text{decode}\rightarrow\text{execute} sequence.

  • Significance

    • Simplifies hardware design; instructions and data fetched through same buses.

    • Foundation for practically every general-purpose computer in use.

Registers

  • General characteristics

    • Fastest, smallest memory locations within the CPU; enable rapid data movement between CPU sub-systems.

  • General-Purpose Registers (GPR)

    • Temporarily store operands or intermediate results accessible by assembly instructions.

  • Special-Purpose Registers (SPR)

    • Hold only one type of information (either data or an address) for specific control tasks.

    • Program Counter (PC): address of next instruction to fetch.

    • Memory Address Register (MAR): address of memory cell to access.

    • Memory Data Register (MDR): data value just fetched from or about to be written to memory.

    • Current Instruction Register (CIR): holds the fetched instruction so that it can be decoded/executed.

    • Accumulator (ACC): destination/source for ALU operations.

    • Index Register (IX): stores an offset used in indexed addressing.

    • Status Register / Flags: stores results of comparisons, overflow, carry, zero, sign, etc.

Processor Components

  • Arithmetic & Logic Unit (ALU)

    • Executes arithmetic (add, subtract) and logical (AND, OR, NOT, compare) operations.

  • Control Unit (CU)

    • Coordinates fetch–decode–execute; issues timing/control signals to ALU, memory, I/O.

  • Immediate Access Store (IAS)

    • Fast memory (often called cache level 0) directly accessible by CPU.

  • System Clock

    • Oscillator producing regular pulses; clock speed measured in \text{GHz} determines max instruction rate.

System Buses

  • Parallel sets of lines that move signals between CPU, memory, I/O.

  • Data Bus (bidirectional)

    • Carries actual data or instructions.

  • Address Bus (unidirectional)

    • Carries the memory/I-O address from CPU to MAR.

  • Control Bus (bidirectional)

    • Carries timing and control signals; prevents contention on data & address buses.

Performance Factors

  • Clock Speed

    • More pulses $\Rightarrow$ more cycles/second $\Rightarrow$ shorter instruction time.

    • Physical limit: heat generation—beyond a point cooling cannot dissipate heat.

  • Bus Width

    • Number of parallel lines \Rightarrow number of bits that move simultaneously (e.g. 32-bit, 64-bit).

  • Cache Size

    • Larger cache stores more frequently used instructions/data, reducing main-memory latency.

  • Number of Cores

    • Multi-core CPUs execute threads in parallel; true concurrency improves throughput.

Ports & Physical Interfaces

  • Purpose: bridge CPU (via motherboard chipset) to external peripherals.

  • USB (Universal Serial Bus)

    • Supports both input & output devices (keyboard, flash drive, printer).

  • HDMI (High-Definition Multimedia Interface)

    • High-bandwidth digital audio/video output only (e.g. monitor, TV).

  • VGA (Video Graphics Array)

    • Analogue video-only output; no audio.

Fetch–Decode–Execute (FDE) Cycle

  1. Fetch

    • \text{MAR} \leftarrow [\text{PC}]

    • \text{PC} \leftarrow [\text{PC}]+1

    • \text{MDR} \leftarrow [[\text{MAR}]] (value at address in MAR)

    • \text{CIR} \leftarrow [\text{MDR}]

  2. Decode

    • CU splits instruction into opcode & operand(s).

  3. Execute

    • CU issues signals so ALU performs operation / registers updated / I-O handled.

  4. Return to step 1.

  • Bracket notation reminder

    • [X] = contents of register X.

    • [[X]] = value stored at memory address contained in X.

Register Transfer Notation (RTN)

  • Example cycle described above; concise formalism used in textbooks & exam answers.

Interrupts

  • Definition: asynchronous signal requesting CPU attention.

  • Types: hardware (I/O, timer), software (exceptions), high vs low priority.

  • Handling sequence

    1. At end of current FDE cycle, CPU polls interrupt register/flag.

    2. If high-priority flag set:

    • Disable further interrupts of same/lower level.

    • Push contents of all registers onto stack.

    • \text{PC} \leftarrow \text{ISR address}; execute ISR.

    • On ISR completion: pop registers, re-enable interrupts, resume main program.

  • Ensures minimal data loss & supports multitasking.

Assembly Language vs Machine Code

  • Assembly

    • Human-readable mnemonics (e.g. ADD, LDD, JMP) + operand.

  • Machine Code

    • Binary patterns executed directly by hardware.

  • One-to-one correspondence: each assembly instruction → exactly one machine instruction.

Symbolic & Absolute Addressing

  • Mnemonics stand in for opcodes.

  • Labels represent addresses; an absolute address is fixed.

Assemblers

  • Converts source (assembly) → object (machine) code.

  • One-Pass Assembler

    • Reads program once; cannot resolve forward references.

  • Two-Pass Assembler

    • Pass 1: builds symbol table; suppresses errors.

    • Pass 2: replaces symbols with addresses; reports errors; outputs machine code.

Instruction Set Overview

  • Data Movement

    • LDM #n – immediate n \rightarrow \text{ACC}.

    • LDD addr – direct (contents at addr) \rightarrow \text{ACC}.

    • LDI addr – indirect (addr contains pointer) \rightarrow \text{ACC}.

    • LDX addr – indexed (addr + IX) \rightarrow \text{ACC}.

    • STO addr – store ACC \rightarrow memory.

  • Arithmetic

    • ADD addr – add memory contents to ACC.

    • INC – \text{ACC} = \text{ACC} + 1.

  • Comparison

    • CMP addr or CMP #n – sets status flags.

  • Conditional Jumps

    • JPE addr – jump if comparison TRUE (equal).

    • JPN addr – jump if comparison FALSE (not equal).

  • Unconditional Jump: JMP addr.

  • I/O

    • IN – read char; ASCII \rightarrow \text{ACC}.

    • OUT – output char whose ASCII in ACC.

  • Program End: END returns control to OS.

Addressing Modes

  • Direct: operand holds actual memory address.

  • Indirect: operand points to a cell containing target address.

  • Indexed: effective address = \text{operand} + \text{IX}.

  • Relative: effective address = \text{PC} + \text{offset} (supports relocatable code).

Bit Manipulation (Shift Operations)

  • Left Shift (LSL #n) ⇒ multiply by 2^{n}.

    • Example: multiply by 4 → shift 2 bits left.

  • Right Shift (LSR #n) ⇒ divide by 2^{n} (integer division).

  • Shift Types

    • Logical Shift: vacated positions filled with 0.

    • Arithmetic Shift: preserves sign bit (MSB) for signed integers.

    • Cyclic (Rotate): bit leaving one end re-enters at opposite end.

Bit Masking & Flag Operations

  • Each bit often acts as an independent flag; masking lets us set, clear, test flags efficiently.

  • Terminology

    • Masking: choose which bits to keep/clear.

    • Set bits to 1 → use OR with mask containing 1s at positions to set.

    • Clear bits to 0 → use AND with mask containing 0s at positions to clear.

    • Matching / Testing

    • AND operand with mask; compare result to expected pattern via CMP.

    • If \text{result} \neq \text{pattern} (non-zero difference) ⇒ mismatch.

  • Practical Steps

    1. Create mask (retain = 1, mask-out = 0).

    2. Apply AND to isolate bits.

    3. Optionally OR with pattern to force certain bits high.

    4. Use CMP or subtract to set status flags for branch decisions.

Ethical & Practical Context

  • Efficient CPU design (multi-core, caching) balances performance vs power vs heat.

  • Ports (USB/HDMI/VGA) exemplify need for standardised, backward-compatible I/O.

  • Understanding assembly & bit manipulation is critical for embedded systems, OS kernels, cybersecurity (exploit mitigation), and compiler optimisation.